Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Huawei Technologies Co., Limited

Yurii Sergeevich Shutkin

Elyar Eldarovich Gasanov

Pavel Anatolyevich Panteleev

Andrey P Sokolov

Ilya Vladimirovich Neznanov

Ivan Leonidovich Mazurenko

Gleb Vyacheslavovich Kalachev

Aleksey Alexandrovich Letunovskiy

Pavel Aleksandrovich Aliseychik

Ilya V Neznanov

Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.

Method and apparatus for encoding and decoding LDPC codes

A base matrix of a rate-adaptive irregular QC-LDPC code is provided, the base matrix being formed by columns and rows having entries representing circulant submatrices. The columns of the base matrix are divided into at least one or more higher weight first columns and lower weight second columns and the rows of the base matrix are divided into first high weight rows corresponding to the high rate mother code and second low weight rows corresponding to the extension part related to the lower rate codes. A first submatrix formed by an intersection of entries of the second columns and entries of the first and the second rows is divided into first quadratic submatrices, wherein at most one entry in each column of each first submatrix and/or at most one entry in each row of each first submatrix is labelled.

Efficiently decodable QC-LDPC code

A receiver configured for use in a communication system, such as a magnetic recording channel, and having a soft-output channel detector provided with a soft-input/soft-output (SISO) modulation codec for parity bits of a block error-correction code. A transmitter of the communication system is configured to encode data by applying a modulation code to the parity bits that have been generated using the block error-correction code. The SISO modulation codec provides an interface between the soft-output channel detector and a parity-check decoder that enables decoding iterations between them in a manner that takes into account inter-bit correlations imposed by the modulation code. In some embodiments, the soft-output channel detector is configured to operate at a fractional rate and to process an input signal carrying non-binary symbols, and the parity-check decoder is configured to apply parity-check-based decoding that is based on a non-binary low-density parity-check code.

Apparatus for processing signals carrying modulation-encoded parity bits

A method of parallel decoding for a plurality of communications standards generally including steps (A) to (C) is disclosed. Step (A) may receive a plurality of first words, at least two of the first words generally have a different length than each other. Step (B) may parse the first words into a plurality of memories. Step (C) may generate a plurality of second words by decoding the first words using a plurality of decoders. The decoders generally operate in parallel. The decoding of at least one of the first words may be performed by at least two of the decoders. The decoding is generally based on a signal that identifies a current one of the communications standards used to transfer the first words.

Parallel decoder for multiple wireless standards

In described embodiments, data streams with irregular patterns are processed by transformations defined by recursively changing processor state, or iteration level. The data transformations are applied to an arbitrary long portion of data, instead of small portions, that are defined directly by a current processor state. Embodiments combine small parts of, for example, puncturing/repetition patterns into a pattern of bigger parts and apply these patterns of bigger parts to relatively large portions of input data.

Optimization of data processors with irregular patterns

An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit may be configured to (i) decode the instructions one at a time and (ii) present a sequence of the commands at an interface. The sequence (i) may be based on the decoding and (ii) may have no delays between consecutive the commands at the interface.

No-delay microsequencer

A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors.

Two-pass linear complexity task scheduler

An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of load values corresponding to a trellis of a decoding process. The second circuit generally includes a plurality of calculation layers. The calculation layers may be configured to generate a plurality of maximum values in response to the load values. The third circuit may be configured to generate a plurality of L-values of the decoding process in response to the maximum values.

L-value generation in a decoder

A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword.

Radix-4 viterbi forward error correction decoding

An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.

Variable parity encoder

A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by adding a plurality of first values related to a plurality of information bits, a plurality of second values related to the information bits and a plurality of third values related to a plurality of parity bits. Step (B) may generate a plurality of permutated values by permutating the sum values based on a configuration signal. The configuration signal generally identifies a current one of the communications standards. Step (C) may generate a plurality of branch metrics values by adding pairs of the permutated values.

Branch metrics calculation for multiple communications standards

An apparatus generally including a first circuit and a second circuit. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard.

Reconfigurable encoding per multiple communications standards

An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address.

Timer manager architecture based on binary heap

An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.

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Moscow, Russia

Yurii Sergeevich Shutkin