International Business Machines Corporation

Globalfoundries Inc.

Globalfoundies Inc.

Yurii A Vlasov

Solomon Assefa

William M Green

Fengnian Xia

Alexander V Rylyakov

Marwan H Khater

William M J Green

Steven M Shank

Tayfun Gokmen

Tymon Barwicz

Jonathan E Proesel

Sharee Jane McNab

Jeehwan Kim

Hendrik F Hamann

Seyoung Kim

Clint Lee Schow

Joris Van Campenhout

Jin-Hong Park

Min Yang

Jessie Carrigan Rosenberg

William Michael John Green

Stephen W Bedell

Steven John Koester

Dennis Merton Newns

Douglas Max Gill

Kuan-Neng Chen

Paul Francis Fortier

Emrah Acar

Saeed Reza Bagheri

Martin Patrick O'Boyle

Petar K Pepeljugoski

Stephane G Harel

Swetha Kamlapurkar

Michael P Beakes

Clint S Schow

Younghee Kim

Ying Di Zhang

Jack Oon Chu

Christopher Vincent Jahnes

Martin Michael Frank

Michael Peter Perrone

Young-Hee Kim

George Gabriel Totir

Young-hee Kim

Gabriel Konrad Dehlinger

Wiliam M Green

Jonathan E Poesel

A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Area and power efficient implementation of resistive processing units using complementary metal oxide semiconductor technology

A device, system, product and method of controlling resistive processing units (RPUs), includes applying an input voltage signal to each node of an array of resistive processing units, and controlling a learning rate of the array of resistive processing units by varying an amplitude of the input voltage signal to the array of resistive processing units. A conductance state of the array of resistive processing units is varied according to the amplitude received at each of the resistive processing units of the array of resistive processing units. The controlling of the amplitude of input voltage signal is according to a processor of a control device.

Voltage control of learning rate for RPU devices for deep neural network training

A neural network system comprises a plurality of neurons, comprising a layer of input neurons, one or more layers of hidden neurons, and a layer of output neurons. The system further comprises a plurality of arrays of weights, each array of weights being configured to receive a plurality of discrete data points from a first layer of neurons and to produce a corresponding discrete data point to a second layer of neurons during a feed forward operation, each array of weights comprising a plurality of resistive processing units (RPU) having respective settable resistances. The system includes a neuron control system configured to control an operation mode of each of the plurality of neurons, wherein the operation mode comprises: a feed forward mode, a back propagation mode, and a weight update mode.

Accelerated neural network training using a pipelined resistive processing unit architecture

An array of resistive processing units (RPUs) comprises a plurality of rows of RPUs and a plurality of columns of RPUs wherein each RPU comprises an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column. A first storage is configured to store a weight value of the RPU, and a second storage is configured to store an amount of change to the weight value of the RPU. When the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the RPU is added to the weight value of the RPU.

Resistive processing units and neural network training methods

Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.

Resistive processing unit

A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide.

Buried waveguide photodetector

The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Method and apparatus for optical modulation

A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion.

Semiconductor photonic package

Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.

Fabrication of localized SOI on localized thick box lateral epitaxial realignment of deposited non-crystalline film on bulk semiconductor substrates for photonics device integration

A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolates the first and second silicon-on-insulator region. Within the STI region, a germanium material is deposited adjacent an end facet of the semiconductor optical waveguide. The germanium material forms an active region that receives propagating optical signals from the end facet of the semiconductor optical waveguide.

Butt-coupled buried waveguide photodetector

A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Stress engineered multi-layers for integration of CMOS and Si nanophotonics

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Katonah, NY, United States of America

Yurii A Vlasov