Toshiba Memory Corporation

Kioxia Corporation

Yuri Terada

Akio Sugahara

Noriyasu Kumazaki

Junichi Sato

Masashi Yamaoka

Yuzuru Shibazaki

Norichika Asaoka

Takaya Handa

Kazuto Uehara

Bushnaq Sanad

Ryosuke Isomura

Masahiro Yoshihara

Yasufumi Kajiyama

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Memory device which generates operation voltages in parallel with reception of an address

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

A semiconductor storage device includes a memory cell array, a temperature sensor configured to generate a first temperature signal corresponding to a temperature of the memory cell array in response to a first command periodically generated during a waiting period of the memory cell array, a storage circuit configured to store the first temperature signal and update the first temperature signal each time the first command is generated during the waiting period, and a voltage generation circuit configured to generate a voltage to be applied to the memory cell array based on the first temperature signal stored in the storage circuit.

Growing community of inventors

Yokohama Kanagawa, Japan

Yuri Terada