Silicon Design Systems Ltd.

Yuri Miroshnik

Anatoli Shindler

Svetlana Yurin

Yzhar Keysar

Methods and apparatus for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit design. Local sensitivity functions at design nodes are aggregated and merged at interconnecting nodes in a recursive process.

Methods and apparatus for validating design changes without propagating the changes throughout the design

An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same

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Naaleh, Israel

Yuri Miroshnik