Sony Semiconductor Solutions Corporation

Sony Corporation

Yuri Kato

Yusuke Oike

Jun Ogi

Masahiro Sato

Kan Shimizu

Naohiko Kimizuka

Machiko Kametani

Yoshihisa Matoba

To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Charge detection sensor and potential measurement system

To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

Semiconductor device and potential measurement apparatus

The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.

Semiconductor apparatus and potential measuring apparatus

The present disclosure relates to a semiconductor device and a cell potential measuring apparatus capable of amplifying and reading a potential of solution with high accuracy. A reading electrode reads the potential of the solution. A differential amplifier includes a current mirror circuit. The reading electrode is connected to a first input terminal of the differential amplifier which is connected to a gate of a first input transistor connected to a diode-connected pMOS transistor of the current mirror circuit. An output terminal of the differential amplifier is connected to a second input terminal of the differential amplifier, which is connected to a gate of a second input transistor connected to a pMOS transistor of the current mirror circuit which is not diode-connected, via a capacitor. For example, the present disclosure is applied to the cell potential measuring apparatus and the like.

Semiconductor device and cell potential measuring apparatus

The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing electrostatic breakdown in an electrode formation process when an electrode and an amplifier are provided on a same substrate. A diode is provided of which a cathode is connected to a previous stage of an amplifying transistor for amplifying a signal read by a read electrode for reading a potential having contact with liquid in which a specimen is input and an anode is grounded. With such a configuration, by bypassing a negative charge generated between the electrode and the amplifying transistor in the electrode formation process from the diode and discharging the negative charge toward ground so as to prevent electrostatic breakdown. This is applicable to a bioelectric potential measuring apparatus.

Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.

DA converter, solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus

The present technology relates to a signal processing device and a method, an imaging device, and an imaging apparatus that are designed to reduce occurrences of A/D conversion errors. A signal processing device of the present technology includes: a comparing unit that compares an analog signal output from a unit pixel with a predetermined voltage; a switching unit that switches reference voltages to be supplied to the comparing unit as necessary, connects one of the reference voltages to the comparing unit, and connects another one of the reference voltages to a predetermined load capacitance, the reference voltages being of different gradation accuracies from each other; and a measuring unit that measures timing of a change in a result of the comparison performed by the comparing unit. The present technique can be applied to imaging devices and imaging apparatuses, for example.

Signal processing device and method, imaging device, and imaging apparatus

DA converter, solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus having a cascade transistor group switch section selecting one of a plurality of cascade transistor groups according to gain setting value set to a current generation section

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Kanagawa, Japan

Yuri Kato