Hewlett Packard Enterprise Development LP

Yupu Zhang

Kimberly Keeton

Haris Volos

Evan Randy Kirshenbaum

Sharad Singhal

Ram Swaminathan

Daniel Juergen Gmach

Milind M Chabbi

Yuvraj Patel

Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.

Concurrent reading and writing with crash recovery in persistent memory

Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.

Programming model and framework for providing resilient parallel tasks

An example system comprises one or more processing nodes to execute one or more processes; a switching fabric coupled to the one or more processing nodes; a fabric-attached memory (FAM) coupled with the switching fabric; and a memory allocator to allocate and release memory in the FAM in response to memory allocation requests and memory release requests from the one or more processes. The memory allocator is to partition the FAM into a memory shelf comprising a plurality of memory books of equal size. The memory allocator is to map a shelf into a virtual memory zone, the zone aligned with the boundaries of one or more books. The memory allocator is to maintain an indexed free-memory list where each index level is an entry point to a list of free memory blocks of a particular size in the zone, and the memory allocator to maintain a bitmap of the zone to identify if a memory block of a particular size is allocated.

Shared fabric attached memory allocator

Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.

Growing community of inventors

Palo Alto, CA, United States of America

Yupu Zhang