International Business Machines Corporation

Globalfoundries Inc.

Yuping Cui

Rasit Onur Topaloglu

Dongbing Shao

James A Culp

Rama Nand Singh

Scott Marshall Mansfield

Geng Han

Shaoning Yao

Atsushi Azuma

Marco Facchini

Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Addressing layout retargeting shortfalls

Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.

Semiconductor layout generation

A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a simulation target that is used as the new target within the MBOPC process. The pattern dependent portion of the model is used as the process model in the MBOPC algorithm. This results final mask designs that result in improved across-chip line width variations, and a more robust MBOPC process.

Method for improving optical proximity correction

A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout. The placement of the SRAFs is verified by: 1) formulating a unique image property using a technology specific representative sample design with and without properly placed SRAFs; 2) simulating the resist image of each individual device layout in the photomask, considering the layout environment of each individual device, and analyzing the unique image properties associated with the device being examined; 3) sorting the geometric properties of each device into predetermined category; and 4) for each individual device layout, examining the image property value and geometric category values, and determining whether the device is adequately surrounded by SRAFs. If not, individual device on the photomask layout are marked with error marker shapes to be subsequently corrected.

Method of verifying the placement of sub-resolution assist features in a photomask layout

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Fishkill, NY, United States of America

Yuping Cui