Via Alliance Semiconductor Co., Ltd.

Yunxing Dong

Zhiqiang Hui

Lin Li

Lingyan Zhong

A host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch buffer set, the control module pre-fetches and buffers data starting from a first address of a storage device into the pre-fetch buffer set and accesses the other buffer set between the first buffer set and the second buffer set to respond to a read request that the central processing unit issues to access data of a second address of the storage device.

Host interface controller and control method for storage device

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

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Beijing, China

Yunxing Dong