Seagate Technology Incorporated

Future Wei Technologies, Inc.

Lsi Corporation

Other

Samsung Electronics Co., Ltd.

Seagate Technology International

Yunxiang Wu

Erich Franz Haratsch

Yu Cai

Zhengang Chen

Earl T Cohen

Ning Chen

Abdelhakim Alhussien

Sundararajan Sankaranarayanan

Abdel-Hakim S Alhussien

Jamal Riani

Xiaobing Lee

Xiangyu Tang

Alexander Hubris

Jeremy Werner

Yu Meng

AbdelHakim S Alhussien

Feng Yang

Christopher Brewer

Yingquan Wu

Timothy Lawrence Canepa

Ivana Djurdjevic

Tom S Chan

Richard Wang

Hakim Alhussien

Henry Bang

Ken Hu

A method performed by a processor to improve wear-leveling in a cross-point (XD) memory, comprises detecting, by a processor coupled to the XD memory, a trigger event, wherein the XD memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.

Wear-leveling method for cross-point memory for multiple data temperature zones

Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

Periodically updating a log likelihood ratio (LLR) table in a flash memory controller

An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.

Hybrid LPDDR4-DRAM with cached NVM and flash-NAND in multi-chip packages for mobile devices

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Systems and methods for latency based data recycling in a solid state memory system

A storage device implements a method for garbage collection. The storage device arranges data blocks of a storage medium into a bin and determines first coldness of a first data block in the bin and second coldness of a second data block in the bin that are respectively associated with a first rate of change of valid data in the first data block into invalid data and a second rate of change of valid data in the second data block into invalid data. Based on the first coldness and the second coldness, the storage device selects a colder data block from the first and second data blocks as a garbage data block. Because the valid data in the selected garbage data block are more stable, they may cause less new stale data or garbage data in a new block to which the valid data are moved.

Garbage collection in storage system

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.

Systems and methods for soft decision generation in a solid state memory system

A method is performed by a solid state device (SSD) controller to generate a parity. The method includes receiving input data to be stored to pages of a storage device, wherein each page is capable of being allocated with multiple codewords; configuring codewords of the pages into multiple groups, wherein each group has an integer number of codewords, at least one of the pages is allocated with a non-integer number of codewords, and wherein the integer number is larger than the non-integer number; obtaining parities for the multiple groups, and storing the parities to reserved spaces of the storage device. With the calculation of a parity decoupled from physical pages, the selection of a rate of code used is unconstrained by an integer number of codewords per page.

Generating parity for storage device

Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages.

Systems and methods for differential message scaling in a decoding process

An apparatus comprises a memory and a controller. The memory generally comprises a plurality of memory modules. The controller may be configured to process a plurality of read/write operations, classify data pages from multiple blocks of the memory as hot-read data or non hot-read data, and aggregate the hot-read data by selecting one or more of the hot-read data pages from multiple memory blocks and mapping the selected hot-read data pages to dedicated hot-read data blocks using a strong type of error correcting code during one or more of a garbage collection state, a data recycling state, or an idle state. The aggregation of the hot-read data pages and use of the strong type of error correcting code reduces read latency of the hot-read data pages, reduces a frequency of data recycling of the hot-read data pages, and reduces an impact of read disturbs on endurance of the memory.

Hot-read data aggregation and code selection

A method of characterizing a distribution of a maximum number of errors that first cause uncorrectable error correction code failure for hard low density parity check codes includes selecting a low density parity check code, generating encoded data with the low density parity check code and writing the encoded data to a number of memory blocks, reading the encoded data from the number of memory blocks and determining any pages having a first uncorrectable error correction code failure, determining a number of raw bit errors for each page having a first uncorrectable error correction code failure, incrementing an error count value corresponding to each of the numbers of raw bit errors determined, and repeating the generating, reading, determining, and incrementing steps for a predetermined range of values of a predetermined reliability statistic of the memory blocks.

Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes

An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.

Flash command that reports a count of cell program failures

An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.

Flash memory read error recovery with soft-decision decode

An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.

Flash channel with selective decoder likelihood dampening

Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a first voltage, programming a second cell of the solid state memory device to a second voltage different than the first voltage, detecting a voltage shift in the first cell when the second cell is being programmed; characterizing the first voltage of the first cell offset by the voltage shift as an interim voltage of the first cell, and repeatedly reading the interim voltage of the first cell using a first set of incrementally adjusted voltage values until an output of the first cell changes.

Systems and methods for sub-zero threshold characterization in a memory cell

An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

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Cupertino, CA, United States of America

Yunxiang Wu