Chengdu Boe Optoelectronics Technology Co., Ltd.

Boe Technology Group Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Yunsheng Xiao

Haigang Qing

Xiangdan Dong

Miao Wang

Tingliang Liu

Jingwen Zhang

Hongwei Ma

Yuqian Pang

Tiaomei Zhang

Ziyang Yu

Zhiliang Jiang

Quanyong Gu

Ming Hu

Shilong Wang

Gukhwan Song

Zhenxiao Tong

Weiyun Huang

Yu Wang

Yue Long

Fan He

Mengqi Wang

Xiaoqing Shu

Yonglin Guo

Bo Zhang

Wenhui Gao

Dan Cao

Zhengwei Luo

Jiping Zhao

Rui Wang

Haijun Qiu

Mengmeng Du

Cong Fan

Rong Wang

Pan Zhao

Wenbo Chen

Hong Yi

Zhongliu Yang

Zhifeng Zhan

Zhengkun Li

De Li

Yang Wang

An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.

Array substrate and display apparatus

A display substrate and a manufacturing method therefor, and a display device are provided. The display substrate includes a drive circuit layer disposed on a substrate, the drive circuit layer includes a plurality of circuit units, at least one circuit unit includes a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line extends along a second direction and is arranged at intervals along a first direction, at least a portion of the data fan-out line is disposed between the first power supply line and the data signal line, the first direction intersects with the second direction.

Display substrate with optimized fan-out structure, preparation method thereof, and display apparatus

A pixel circuit includes a driving sub-circuit coupled to a first node, a second node and a third node, a compensation sub-circuit coupled to the first node, the third node and a first scan signal terminal, an adjustment sub-circuit, and a writing sub-circuit. The compensation sub-circuit includes a first transistor group, and the first transistor group includes at least two first transistors connected in series. A fourth node is formed between a second electrode of a first first transistor and a first electrode of a second first transistor. The adjustment sub-circuit is coupled to the fourth node and at least one control terminal. The adjustment sub-circuit is configured to, in light-emitting phases, adjust a voltage of the fourth node under a control of a signal from the at least one control terminal, so as to reduce a voltage difference between the fourth node and the first node.

Pixel circuit and driving method thereof, and display panel

A pixel driving circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit and an adjustment sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node. The writing sub-circuit is coupled to the second node, a first scan signal terminal and a data signal terminal. The compensation sub-circuit is coupled to the first node, the third node and a compensation control terminal. The adjustment sub-circuit is coupled to the second node and/or the third node, a second scan signal terminal and a first reference voltage signal terminal. The adjustment sub-circuit is configured to, in a light-emitting adjustment phase, transmit a reference voltage signal received at the first reference voltage signal terminal to the second node and/or the third node under control of a scan signal transmitted by the second scan signal terminal.

Pixel driving circuit and driving method thereof, and display panel

A display substrate and a display apparatus are provided, and the display substrate includes a pixel circuit with a light emitting module configured to emit light; a driving module configured to drive the light emitting module to emit light based on a driving voltage in a luminescence stage; a storage module configured to maintain and provide the driving voltage to the driving module in the luminescence stage; a first transistor, having a first electrode coupled to a position from which the driving module acquires the driving voltage; a second transistor, having a first electrode coupled to the first electrode of the first transistor, and a second electrode being not directly coupled to a signal source; and a voltage stabilizing capacitor, having a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to a constant voltage signal source.

Display substrate and display apparatus

A display substrate and a driving method therefor, and a display device. The display substrate comprises a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, which at least comprises a compensation transistor, a driving transistor, a data writing transistor, a first storage capacitor, and a second storage capacitor, wherein a gate electrode of the data writing transistor is connected to a first scan signal line; a gate electrode of the compensation transistor is connected to a second scan signal line; a first end of the first storage capacitor is connected to a gate electrode of the driving transistor; a first end of the second storage capacitor is connected to a first electrode of the driving transistor; and a second end of the first storage capacitor and a second end of the second storage capacitor are connected to a first power line.

Display substrate and driving method therefor, and display device

A display substrate and a preparation method thereof, and a display apparatus is provided in the present disclosure. The display substrate include a drive circuit layer disposed on the substrate, the drive circuit layer includes a plurality of circuit units, the circuit units include a pixel drive circuit and a data signal wire providing a data signal to the pixel drive circuit and an initial signal wire providing an initial signal; the plurality of circuit units includes at least one normal circuit unit and at least one tracing circuit unit, the normal circuit unit is provided with a first compensation line extending along a first direction and a second compensation line extending along a second direction.

Display substrate and preparation method thereof, display apparatus

A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.

Display panel with gate driving circuit including shift register units

A display substrate is disclosed, including a display area and a non-display area. The non-display area has a gate drive circuit including multiple cascaded shift register units. A shift register unit includes an input control circuit and an output circuit. The input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and an output circuit, the output circuit is electrically connected to the first power supply line and a second power supply line. The input control circuit at least includes an input circuit and a first control circuit. The clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction. The input circuit is located between the second power supply line and the first control circuit in the first direction.

Display substrate, manufacturing method therefor, and display apparatus

A shift register includes a first control circuit configured to, according to one of a second clock signal and a first voltage signal, control a voltage of a second node under control of a voltage of the first node and the second clock signal; and a holding circuit configured to transmit the first voltage signal to an output signal terminal under control of the voltage of the second node. The first control circuit includes a third transistor and a second capacitor. A control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first voltage signal terminal, and a second electrode of the third transistor is electrically connected to a third node. First and second ends of the second capacitor are electrically connected to the second clock signal terminal and the third node, respectively.

Shift register with input circuit, output circuit and potential stabilization circuit, method of driving the same, scan driving circuit and display device

A display substrate includes a source-drain metal layer and a common electrode layer. A pattern of the source-drain metal layer includes a power supply voltage line; the power supply voltage line includes a wire inlet portion; the display substrate further includes a barrier wall, there is a gap between an orthographic projection of the barrier wall on the base substrate and an orthographic projection of the effective display area on the base substrate. The wire inlet portion includes a first part and a second part; an orthographic projection of the first part on the base substrate and an orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at a side of the barrier wall away from the effective display area and located between the barrier wall and the binding area, and used for receiving power supply voltage signal.

Display substrate, display panel and display device

A pixel circuit includes a data writing sub-circuit, a driving sub-circuit, and one or more potential maintenance sub-circuits. The data writing sub-circuit is coupled to at least a first voltage signal terminal, a data signal terminal, a first scan signal terminal and a first node, and writes a data signal provided by the data signal terminal into the first node under control of at least a first scan signal provided by the first scan signal terminal. The driving sub-circuit is coupled to the first node, a second node and a third node, and creates a path between the second node and the third node under control of a potential at the first node. A potential maintenance sub-circuit is coupled to a circuit node and a reference signal terminal, and maintains a potential at the circuit node through a reference signal provided by the reference signal terminal.

Pixel circuit and driving method thereof, display panel, and display apparatus

The present disclosure provides a shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor; the second transistor has a first electrode coupled to a second node; the third transistor has a first electrode coupled to a first power terminal and a second electrode coupled to the second node; the fifth transistor has a control electrode coupled to a third node; and the impedance transistor has a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node.

Shift register, driving circuit and display substrate

A display panel, a driving method, and a display device. The display panel includes: a base substrate, subpixels, driving lines, data lines, a gate driving circuit including clock signal lines and shift register units arranged in extension direction of clock signal lines. The clock signal lines is divided into clock signal line groups; the shift register units is divided into register unit groups; the shift register units in same register unit group are cascaded, adjacent two of shift register units in the extension direction are in different register unit groups; one register unit group corresponds to one clock signal line group; the gate of an input transistor is connected to a clock signal line in a corresponding clock signal line group, the second pole of input transistor is connected to the gate of an output transistor; the second pole of output transistor is connected to at least one driving line.

Display panel, driving method, and display device

A display substrate and a display device are provided. The display substrate includes a base substrate, multiple sub-pixels, multiple data lines, a test circuit, multiple data leads, at least one test pad, and at least one first test signal line. The multiple data lines are electrically connected to the multiple sub-pixels, and configured to provide data signals to the multiple sub-pixels. The multiple data leads are electrically connected to the multiple data lines and the test circuit. At least one test pad is located on at least one side of the test circuit. The at least one first test signal line is electrically connected to at least one test pad and the test circuit, and includes at least two conductive layers connected in parallel and electrically connected to each other.

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Beijing, China

Yunsheng Xiao