Texas Instruments Corporation

Yunlong Liu

Hong Yang

Yufei Xiong

Seetharaman Sridhar

Manoj K Jain

Ya Ping Chen

Furen Lin

Frank Alexander Baiocchi

Sunglyong Kim

Zachary K Lee

He Lin

Fei Ma

Ho Lin

Jiao Jia

Lark Liu

Rui Liu

Jianxin Liu

Chao Zuo

Shengpin Yang

Tianping Lv

Zhi Peng Feng

Abbas Ali

Peng Hu

Haian Lin

Peng Li

Jing Hu

Sheng Zou

Zhipeng Feng

Wei Tang

Wei Song

ZiQiang Zhao

Peter Lin

Yaping Chen

Christopher Boguslaw Kocon

Hideaki Kawahara

Michael F Chisholm

Qiuling Jia

Chao Zhuang

Tian Ping Lv

Qiu Ling Jia

Rui Song

Baoqiang Niu

Dongsheng Liu

In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Multi-layer polysilicon stack for semiconductor devices

A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Reduced ESR in trench capacitor

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Trench shield isolation layer

In a semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Method of fabricating a tungsten plug in a semiconductor device

A method () of fabricating a semiconductor device includes etching () a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed () in the group of trenches and the dielectric liner is etched () in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled () with a polysilicon layer.

Dual shield oxide damage control

A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.

Semiconductor device including a lateral insulator

A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

Trench capacitor with warpage reduction

A trench gate metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial layer on a substrate both doped a first conductivity type. Active area trenches have polysilicon gates over a double shield field plate. A junction termination trench includes a single shield field plate in a junction termination area which encloses the active area that includes a retrograde dopant profile of the second conductivity type into the epitaxial layer in the junction termination area. Pbody regions of a second conductivity type are between active trenches and between the outermost active trench and the junction termination trench. Source regions of the first conductivity type are in the body regions between adjacent active trenches. Metal contacts are over contact apertures that extend through a pre-metal dielectric layer reaching the body region under the source region, the single shield field plate, and that couples together the polysilicon gates.

Vertical trench gate MOSFET with deep well region for junction termination

In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

Transistor device with sinker contacts and methods for manufacturing the same

A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Power MOSFET with metal filled deep sinker contact for CSP

A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

Power MOSFET with a deep source contact

A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

Integrated trench capacitor formed in an epitaxial layer

A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

Semiconductor device having polysilicon field plate for power MOSFETs

A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of &#x3e;3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

Power MOSFET with metal filled deep source contact

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Chengdu, China

Yunlong Liu