Huawei Technologies Co., Limited

Yunlei Qi

Xinyuan Wang

Tao Lin

Xiang He

Junmin Song

Chunrong Li

Hongwei Niu

Song Liu

Jingfeng Chen

Jinhui Wang

Liqing Chen

Yongjian Hu

This application provides a communication method and an optical module. The method includes: A first optical module determines a first delay. The first optical module sends the first delay to an interface chip. According to the communication method and the optical module that are provided in this application, a delay in the optical module can be reported to the interface chip, so as to improve precision of time synchronization between a master clock and a slave clock, thereby further improving clock precision of a network device.

Communication method and optical module

A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

Clock synchronization method and apparatus

This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

Method and apparatus for sending and receiving clock synchronization packet

A device determines a first latency value of a first data flow from a first physical port of the device to a second physical port of the device and a second latency value of a second data flow from the second physical port to the first physical port, where the first latency value is less than the second latency value. The device determines a first target latency value based on the first latency value and the second latency value. The device adjusts a latency value of the first data flow to the first target latency value.

Latency compensation method and device

A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and where the second packet is the first packet processed by the media conversion module, and calculating a time interval Tbetween a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the Tis used to compensate for a first timestamp at which the first network device receives or sends the third packet.

Packet processing method and network device

This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

A time synchronization method includes receiving, by a receive-end device, a first timestamp and a first header signal sent by a transmit-end device, where the first timestamp indicates a first moment at which a first channel medium conversion module sends the first header signal, and a second moment at which the receive-end device receives the first header signal. The method further includes sending a second header signal to the transmit-end device, where a third moment at which the receive-end device sends the second header signal. The method further includes receiving a fourth timestamp sent by the transmit-end device, where the fourth timestamp indicates a fourth moment at which the transmit-end device receives the second header signal. The method further includes synchronizing time with the transmit-end device based on the first moment, the second moment, the third moment, and the fourth moment.

Time synchronization method and device

A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and the second packet is the first packet processed by the media conversion module, and calculating a time interval Tbetween a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the Tis used to compensate for a first timestamp at which the first network device receives or sends the third packet.

A packet processing method includes: obtaining, at a Medium Access Control (MAC) layer, a first fragmented data frame included in a first data frame; buffering the first fragmented data frame into a first queue; obtaining, at the MAC layer, a second fragmented data frame included in a second data frame; buffering the second fragmented data frame into a second queue; sending the first fragmented data frame to a forwarding processing module; obtaining first forwarding information using the forwarding processing module; sending the second fragmented data frame to the forwarding processing module after sending the first fragmented data frame to the forwarding processing module; and obtaining second forwarding information.

Packet processing based on latency sensitivity

A communications network delay variation smoothing method, an apparatus, and a system are disclosed. The method includes: clearing, by a local device, a forward delay threshold and a reverse delay threshold when an initialization time starts; and when determining that a maximum value between a real-time forward delay value corresponding to a current service flow fragment and a reverse delay threshold corresponding to the current service flow fragment is greater than a current value of the forward delay threshold, replacing the current value of the forward delay threshold with the maximum value. In this way, after the initialization ends, a delay threshold after the initialization ends is determined and is applied to delay compensation, thereby significantly reducing a bi-directional asymmetric delay variation, and avoiding a problem of abnormal user communication that is caused when the variation exceeds a limit.

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Dongguan, China

Yunlei Qi