Samsung Electronics Co., Ltd.

Yunkyo Cho

Sehwan Lee

Junseok Park

Joonho Song

Junwoo Jang

Jinook Song

Daekyeung Kim

An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

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Suwon-si, South Korea

Yunkyo Cho