Micron Technology Incorporated

Intel Corporation

Yunjun Ho

James Mathew

H Jim Fulford

Brent D Gilgen

Jie Sun

Brett D Lowe

Zhiqiang Xie

Hyun Sik Kim

Zhaoli Sun

Kevin L Beaman

Matt Meyers

Gregory J Light

A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

Slit stress modulation in semiconductor substrates

A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.

A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500&#xb0; C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800&#xb0; C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation

A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% HO by volume. A polysilazane-comprising spin-on dielectric material is formed onto the HO-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

Methods of forming silicon oxides and methods of forming interlevel dielectrics

Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500&#xb0; C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700&#xb0; C. to about 1000&#xb0; C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.

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Boise, ID, United States of America

Yunjun Ho