Samsung Electronics Co., Ltd.

Yunhyeok Im

Kyol Park

Heeseok Lee

Jichul Kim

Youngsang Cho

Eon Soo Jang

Kyoung-Min Lee

Kyungsoo Lee

Horang Jang

Moonseob Jeong

Dongsuk Shin

Sang Il Kim

Jongwoo Park

Youngbae Kim

Taeje Cho

Soojae Park

Oleg Feygenson

Jin-Kwon Bae

Mi-Na Choi

Seungkon Mok

Seongho Shin

Byungsu Kim

Jungsu Ha

Seran Bae

Inhwan Baek

A semiconductor package includes a first interconnection structure, a first semiconductor chip disposed on the first interconnection structure and including a plurality of through-vias and first pads connected to the plurality of through-vias; a second semiconductor chip disposed on the first interconnection structure, including second pads electrically connected to the first pads, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding side surfaces of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having higher thermal conductivity than a thermal conductivity of silicon; and an encapsulant surrounding side surfaces of the heat dissipating structure.

Semiconductor package having improved heat dissipation characteristics

A semiconductor package includes a first substrate, a semiconductor chip disposed on the first substrate, a mold layer disposed on the first substrate and at least partially covering the semiconductor chip, and a heat dissipation structure disposed on a first top surface of the semiconductor chip and in the mold layer. The heat dissipation structure covers an inner side surface of the mold layer. A surface roughness of the first top surface of the semiconductor chip is greater than a surface roughness of a side surface of the semiconductor chip, and a surface roughness of the inner side surface of the mold layer is greater than a surface roughness of a top surface of the mold layer. The heat dissipation structure includes voids therein.

Semiconductor package including a heat dissipation structure

The present disclosure provides a device and methods to control a temperature of an integrated circuit (IC). For example, a device may include a circuit (e.g., an IC), a power monitor, a temperature sensor, and a controller. In some examples, temperature may be estimated based on power measured by a dynamic power monitor (DPM). In some cases, the estimated temperatures may be corrected based on temperature sensed by a temperature sensor on the IC. The power may be measured in shorter time periods and/or more frequent time periods compared to a time periods that the temperature sensor senses temperature. Accordingly, the temperature of an IC may be detected and adjusted more frequently based on the power measurements, and the temperature estimates may be adjusted for accuracy based on sensed temperatures.

Method and device for temperature detection and thermal management based on power measurement

A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

Semiconductor package including composite molding structure

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

Semiconductor package

A semiconductor module may include a substrate including a first region and a second region, a first chip mounted in the first region, a second chip and passive devices mounted in the second region, and a heat dissipation layer being in contact with a top surface of the first chip. The heat dissipation layer may be provided on top surfaces and side surfaces of the first chip, the second chip and the passive devices.

Semiconductor module including heat dissipation layer

A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.

Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.

Packaged semiconductor chips having heat dissipation layers and ground contacts therein

The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Package-on-package device

According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Semiconductor packages including heat exhaust part

A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame.

Semiconductor package and method for manufacturing the same

In a package-on-package (PoP) device according to the inventive concepts, an anisotropic conductive film is disposed between a lower semiconductor package and an upper semiconductor package to remove an air gap between the lower and upper semiconductor packages. Thus, heat generated from a lower semiconductor chip may be rapidly and smoothly transmitted toward the upper semiconductor package, thereby increasing or maximizing a heat exhaust effect of the PoP device.

Growing community of inventors

Hwaseong-si, South Korea

Yunhyeok Im