Samsung Electronics Co., Ltd.

Yunhwan Kim

Kyohyeok Kim

Sungjin Kim

Seungbo Shim

Dougyong Sung

Jongwoo Sun

Jiwoong Kim

Yongwoo Lee

Jongkeun Lee

Jaehak Lee

Dowon Kim

Minyoung Hur

Byeongsang Kim

Jewoo Han

Moonki Jang

Youngjin Noh

Kuihyun Yoon

Akira Koshiishi

Naohiko Okunishi

Masato Horiguchi

Taeil Cho

Myeongwhan Hyun

Inseok Seo

An impedance measurement jig may include a first contact plate, a second contact plate, a cover plate, a plug, and an analyzer. The first contact plate may make electrical contact with an ESC in a substrate-processing apparatus. The second contact plate may make electrical contact with a focus ring configured to surround the ESC. The cover plate may be configured to cover an upper surface of the substrate-processing apparatus. The plug may be installed at the cover plate to selectively make contact with the first contact plate or the second contact plate. The analyzer may individually apply a power to the first contact plate and the second contact plate through the plug to measure an impedance of the ESC and an impedance of the focus ring. Thus, the impedances of the ESC and the focus ring may be individually measured to inspect the ESC and/or the focus ring.

Impedance measurement jig and method of controlling a substrate-processing apparatus using the jig

A memory device includes a row decoder that receives one or more normal addresses and one or more control addresses, and a memory cell array connected to the row decoder via a plurality of word lines. In a normal operation, in response to receiving the one or more normal addresses, any one word line among the plurality of word lines is enabled. In an initialization operation, in response to receiving the one or more normal addresses and the one or more control addresses, at least two word lines among the plurality of word lines are enabled. Data of memory cells of the memory cell array connected to the enabled at least two word lines is initialized.

Memory device and data initialization method of the same

An etching apparatus includes a reaction chamber having an internal space; an upper electrode in the reaction chamber; a fixing chuck in the internal space of the reaction chamber and below the upper electrode; an electrostatic chuck above the fixing chuck and on which a wafer is configured to be placed; a focus ring surrounding the electrostatic chuck; and a plurality of sealing members configured to seal cooling gas provided to the focus ring and being in contact with the focus ring. The plurality of sealing members may be formed of a porous material. Each of the plurality of sealing members may include a body portion and an outer surface surrounding the body portion. Only the body portion may include voids and the outer surface may be smooth and free of voids.

Etching apparatus

A plasma processing apparatus includes a chamber, a lower and upper electrodes vertically spaced apart from each other in the chamber, a RF transmitting part connected to the lower electrode and configured to supply RF power to the lower electrode, a ground plate spaced downwardly from the lower electrode, and an insulating member laterally surrounding a cavity formed between the lower electrode and the ground plate. The cavity is isolated from a region under the ground plate by the ground plate.

Plasma processing apparatus and method of manufacturing semiconductor device using the same

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Hwaseong-si, South Korea

Yunhwan Kim