Samsung Electronics Co., Ltd.

Yungi Kim

Kangyoon Lee

Jaeman Yoon

Youngwoong Son

Hyeoungwon Seo

Soohan Choi

Byeongyeol Kim

An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, din the inner region, and d' in the intermediate region, where d&#x3c;d

Interconnection architecture for semiconductor device

An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2' in the intermediate region, where d2&#x3c;d2&#x2032;.

An electrode structure, e.g., a gate electrode for a transistor, includes: a volume of semiconductor material; a gate oxide on the semiconductor volume; a barrier layer, including silicon nitride, on the gate oxide layer; an adhesion layer on the barrier layer; and a metallic layer on the adhesion layer.

Gate electrode structure

There is disclosed in the present invention a method for manufacturing a semiconductor device including an isolation region defined by trenches having different or equal widths respectively on a single semiconductor substrate comprising the steps of:

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Gyeonggi-do, South Korea

Yungi Kim