Mediatek Corporation

Industrial Technology Research Institute

Yung-Yu Lin

Hsin-Hung Chen

Hsiang-Hui Chang

Sheng-Jui Huang

Chun-Pang Wu

Jong-Woei Chen

Tse-Hsiang Hsu

Chih-Cheng Chen

Hao-Ping Hong

Jen-Che Tsai

Tzueng-Yau Lin

Hsueh-Wu Kao

Yau-Wai Wong

Chi-Hui Wang

Po-Chin Hsu

Chih-Pin Sun

Kun-Hsien Li

Shu-Kuang Chou

Chih-Horng Weng

An amplitude modulation circuit in a polar transmitter includes a digital-to-analog converter (DAC), a filter, a gm stage, and a calibration module. The DAC is arranged to be coupled to an amplitude modulation signal input in a normal mode. The filter is coupled to the DAC, and the gm stage is coupled to the filter. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. A method for calibrating an amplitude offset in the polar transmitter includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Amplitude modulation circuit in polar transmitter and method for calibrating amplitude offset in polar transmitter

A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced.

Signal processing system having a plurality of high-voltage functional blocks integrated into interface module and method thereof

An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.

Operating circuit

In a continuous-time sigma-delta modulator, by using dynamic element matching (DEM) with respect to comparators of a quantizer, or by generating a plurality of candidate DEM results in advance for selecting an approximate DEM result, a time slot for DEM operations in each cycle of a sampling signal is significantly increased without being rushed.

Continuous-time sigma-delta modulator using dynamic element matching having low latency and dynamic element matching method thereof

An offset calibration system of a control loop at least comprises an optical-to-electrical converter and an electrical-to-optical converter. The optical-to-electrical converter generates a pre-output signal and then transmits the pre-output signal to the electrical-to-optical converter to amplify. The offset calibration system comprises a comparator, an offset calibration module, and a determination circuit. The comparator compares the pre-output signal with a predetermined pre-reference signal to generate a pre-compared signal. The offset calibration module stores a predetermined and adjustable offset calibration value for adding to the pre-output signal. The determination circuit adjusts the offset calibration value based on the pre-compared signal, so the offset calibration value can be added to the pre-output signal dynamically to compensate and calibrate the offset of the pre-output signal caused by the optical-to-electrical converter to avoid the electrical-to-optical converter amplifying the offset of the pre-output signal again.

Offset calibration system and method of automatic power control loop

A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.

Peak detection circuit with double peak detection stages

An offset calibration system of a control loop at least comprises a pre-amplifier circuit and a post-amplifier circuit. The pre-amplifier circuit generates a pre-output signal and then transmits the pre-output signal to the post-amplifier circuit to amplify. The offset calibration system comprises a comparator, an offset calibration module, and a determination circuit. The comparator compares the pre-output signal with a predetermined pre-reference signal to generate a pre-compared signal. The offset calibration module stores a predetermined and adjustable offset calibration value for adding to the pre-output signal. The determination circuit adjusts the offset calibration value based on the pre-compared signal, so the offset calibration value can be added to the pre-output signal dynamically to compensate and calibrate the offset of the pre-output signal caused by the pre-amplifier circuit to avoid the post-amplifier circuit amplifying the offset of the pre-output signal again.

An analog to digital converter for the conversion of an analog input signal to a digital output code of n bits has a plurality of voltage references created in a voltage reference generator that divides the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into most significant bits and least significant bits. The most significant bits are encoded from a set of digital signals that are formed in a set of coarse comparators, that compare the analog input signal with a subset of the voltage references representing the coarse range. The digital code that is the output of the coarse comparators is used to determine the selection of the subset of the plurality of the voltage references that are the fine voltage references. The least significant bits are encoded from a set of digital signals that are formed in a set of fine comparators that compare the analog input signal to the fine voltage references. The digital codes that form the most significant bits and the least significant bits are corrected encoded in an output encoder to form the digital output word.

Two stage analoge-to-digital converter having unique fine encoding

An analog to digital converter for the conversion of an analog input signal to a digital output code is disclosed. The analog to digital converter has a voltage reference generator to create a plurality of voltage references that divides the total conversion range of the input into increments equal to the smallest resolution increment. The digital output code is divided into most significant bits, intermediate significant bits and least significant bits. The most significant bits are encoded from a set of coarse digital signals that are formed in a set of coarse comparators. The coarse digital code is used to determine the selection of the sub-coarse voltage references. The intermediate significant bits are encoded from a set of subcoarse digital signals. The subcoarse digital code that and the coarse digital code are used to determine the selection of the fine voltage references. The least significant bits and a correction factor for the intermediate significant bits are encoded from a set of fine digital signals. The digital codes that form the most significant bits, the intermediate bits, the fine bits, and the correction factor are encoded in an output encoder to form the digital output word.

Growing community of inventors

Taipei, Taiwan

Yung-Yu Lin