Cadence Design Systems, Inc.

Verplex Systems, Inc.

Yung-Te Lai

Chih-Chang Lin

Manish Pandey

Kei-Yong Khoo

Chioumin M Chang

Bret Siarowski

Kung-Chien Chen

Bret Siarkowski

Cheng-Ta Hsieh

Yifeng Wang

Some aspects provide determination of a function to rectify functional differences between netlist Gand netlist Ghaving inputs V. The determination may include determination of a signal s of netlist Gthat can be re-synthesized so as to correct the functional differences between netlist Gand netlist G, assignment of respective static values to a first plurality of inputs V, assignment of respective initial values to a second plurality of inputs V, determination of a first function based on the assigned static values, the assigned initial values, a first error function reflecting the difference between outputs of netlist Gand netlist Gfor each vector of inputs V in a case that s equals 0, and a second error function reflecting the difference between the outputs of netlist Gand netlist Gfor each vector of inputs V in a case that s equals 1. Also included may be determination of whether the first function rectifies the functional differences between netlist Gand netlist G, assignment, if it is determined that the first function does not rectify the functional differences, of respective next values to the second plurality of inputs, and determination of a second function based on the first function, the assigned static values, the assigned next values, the first error function, and the second error function.

Determination of single-fix rectification function

Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Method and system for logic equivalence checking

An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Combinational equivalence checking methods and systems with internal don't cares

An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuits are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Growing community of inventors

Cupertino, CA, United States of America

Yung-Te Lai