Chartered Semiconductor Manufacturing Ltd (corporation)

Yung Tao Lin

Weining Li

Siow Lee Chwa

Wei Li

Tommy Mau Lam Lai

A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

Method of angle implant to improve transistor reverse narrow width effect

A trench transistor formation method for creating source and drain regions and source and drain extension regions having an idealized doping profile using a single dopant implantation step. In one embodiment, the present invention is comprised of a method which includes forming a trench having sidewalls and a bottom into a substrate. The present embodiment also recites forming sidewalls spacer regions along at least a portion of the sidewalls of the trench. Subsequently, the present embodiment forms a gate dielectric along at least a portion of the bottom of the trench, and deposits a gate metal within the trench. The present embodiment then subjects the substrate to an etching process such that the top surface of the substrate is lower than the top surface of the sidewall spacer regions formed along the sidewalls of the trench. The present embodiment then performs a single dopant implantation step which results in the formation of both the source and drain regions and the source and drain extension regions wherein the source and drain regions have an implantation depth which is greater than the implantation depth of the source and drain extension regions. Additionally, substantially no dopant is implanted within a channel region residing beneath the gate metal disposed within the trench. In so doing, an idealized dopant profile is achieved within the trench transistor using the single dopant implantation step.

Trench transistor structure and formation method

A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions. The integrated circuit device is annealed to react the metal layer and the polysilicon layer and silicon to selectively form a silicide layer in the surface of the polysilicon layer and in the surface of the semiconductor substrate at the contact surfaces. The remaining metal layer is removed to complete the device.

Method to form self-aligned silicide with reduced sheet resistance

A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gatedevice including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer.

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Singapore, Singapore

Yung Tao Lin