Taiwan Semiconductor Manufacturing Comp. Ltd.

Yung-Sheng Huang

Hung-Chang Hsieh

Nun-Sian Tsai

Ruey-Lian Hwang

Yu-Ting Lin

Yian-Liang Kuo

Yu-Wen Lin

Chih-Kuang Kao

Huei-Wen Yang

Han-Chang Hsieh

Hui Yu Lee

Jian-Hong Lin

Long-Sheng Yeou

Yung-Huei Lee

Hsin-Chun Chang

Ji-Chung Huang

Chang-Song Lin

Chien-Yi Chen

Chun-Hung Lu

Chin-Cheng Chiu

Chiu-Ching Lin

A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.

Semiconductor device, layout pattern and method for manufacturing an integrated circuit

A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Barrier layer for copper interconnect

A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.

Protecting sidewalls of semiconductor chips using insulation films

A method of forming a heat spreader ball grid array package, and the resultant heat spreader ball grid array package, comprising the following steps. A semiconductor chip affixed to a ball grid substrate is provided. The semiconductor chip over the ball grid substrate is encased with a molding compound. A heat spreader is mounted over the ball grid substrate and spaced apart from the molding compound to form a gap. Thermal grease is placed into the gap, at least between the heat spreader and the molding compound, to form the heat spreader ball grid array package. It is also possible to place thermal grease over the molding compound and then mounting the heat spreader over the ball grid substrate.

Heat spreader ball grid array (HSBGA) design for low-k integrated circuits (IC)

A tool for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Method and apparatus for placing identifying mark on semiconductor wafer

A tool and method for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Method for placing identifying mark on semiconductor wafer

A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed. The process features the use of a tungsten mesh pattern, formed in an IMD layer, and located underlying the bond pad structure, while overlying, and contacting, an underlying upper level, metal interconnect structure. The use of a tungsten mesh pattern, in place of individual tungsten studs, results in the creation of isolated islands, of IMED, reducing the bonding force, experienced by the IMD shapes, during the subsequent gold wire bond procedure. In addition the tungsten mesh pattern is formed via partial filling of a mesh pattern opening, in the IMD layer, resulting in an indented, or notched top surface. This in turn allows a roughened top surface, for the overlying bond pad structure, to be created, resulting in improved bondability of the gold wire, to the roughened top surface of the bond pad structure.

Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability

A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.

Deep-submicron integrated circuit package for improving bondability

A micro-cleavage method for preparing a semiconductor specimen for examination by an optical or electron microscopic is disclosed. The method can be carried out by hand and thus no expensive equipment such as a polishing machine is necessary. In the method, at least two bird's beak marks are cut in a top surface of a silicon wafer that contains a target, i.e., a defect or a circuit to be examined. The bird's beak marks are formed by a wide scribe line and a narrow scribe line overlapped together. The wide scribe line of the bird's beak mark is used for visual alignment with the edge of a rigid substrate, while the fine scribe line is utilized for initiating a crack when a bending stress is applied on the bird's beak mark. The bird's beak mark can be made by using a laser cutter after a wafer slice which contains the target area is first cleaved by mechanical means such as a diamond knife. A first bird's beak mark is formed at the cleaved edge of the slice and a second bird's beak mark is formed with its fine scribe line oriented toward the target. When a bending stress is applied on the top surface of the silicon slice, stress concentrates on the bird's beak marks and creates a fine crack to propagate along a crystallographic plane in the wafer toward the target thus exposing the target in a fractured surface.

Micro-cleavage method for specimen preparation

Method for improving bondability for deep-submicron integrated circuit

A new method of preparing for inspection a wafer having multilayer interconnections is described. Semiconductor device structures having multilayer interconnections are provided in and on a semiconductor substrate wherein the multilayer interconnections comprise alternating layers of oxide interlevel dielectric layers and conducting layers and wherein interconnections are made between the conducting layers through the interlevel dielectric layers and wherein a non-oxide passivation layer overlies the topmost dielectric layer. The non-oxide passivation layer is removed and an oxide passivation layer is deposited overlying the topmost dielectric layer. The oxide passivation layer and interlevel dielectric layers and conducting layers are cut through to expose a sidewall to reveal the multilayer interconnections. The interlevel dielectric layers between conducting layers in the area of the exposed sidewall are removed to complete preparation for observing the semiconductor wafer having multilayer interconnections.

Method to reveal the architecture of multilayer interconnectors in

A method for fabricating seamless, tungsten filled, small diameter contact holes, has been developed. The process features initially creating a tungsten plug, in the small diameter contact hole, and filling or repairing, seams or voids in the tungsten plug, with an additional layer of selectively deposited tungsten.

Process for removing seams in tungsten plugs

A novel method is presented to form and planarize an inter-metal-dielectric(IMD) layer of an integrated circuit with two or more levels of interconnection metallurgy. The method utilizes chemical-mechanical-polishing(CMP) followed by reactive-ion-etching(RIE) to first planarize and then etch back a deposited IMD layer. Metal line spacings of less than 1.5 microns produce voids in the IMD even when spin-on-glass(SOG) is used to partially fill the spaces prior to IMD deposition. These voids, which contain organic residues and debris, can produce eruptions of material during several subsequent processing steps. The method of this invention attenuates and de-activates these voids, rendering them completely benign. Since CMP is only used to achieve a planar surface, risks of CMP damage to alignment marks and other features are also reduced.

Two-step planarization process using chemical-mechanical polishing and

A process for filling small diameter contact holes, with tungsten, has been developed. This process consists of using two consecutive tungsten depositions. A first tungsten layer, that will exhibit a fast removal rate in a specific dry etch chemistry, such as RIE, is used to coat the sidewalls of the small diameter contact hole. Next a second layer of tungsten, that will exhibit a significantly slower removal rate then the first tungsten layer, is used to completely fill the contact hole. Etchback, to remove unwanted material from areas outside the contact hole, does not significantly attack the second tungsten fill, in the contact hole, thus not aggravating any seams in the second tungsten fill that may have been created during the LPCVD tungsten, contact hole fill process.

Growing community of inventors

Hsin-Chu, Taiwan

Yung-Sheng Huang