Mstar Semiconductor, Inc.

Optonomous Technologies, Inc.

Yung Peng Chang

Chung-Ching Chen

Chen-Nan Lin

Mark Chang

Lion Wang

Andy Chen

Kirk Huang

Alan Wang

Kenneth Li

Jian-Kao Chen

Zong-Han Wu

Qi-Xin Chang

An illumination system includes: a laser array assembly including: a laser configured to generate a laser light; a crystal phosphor waveguide, adjacent to the laser and in the laser light, configured to: generate of a luminescent light based on receiving the laser light, and direct the luminescent light away from a base end; and a compound parabolic concentrator (CPC), coupled to the crystal phosphor waveguide opposite the base end, configured to: collect the luminescent light from the crystal phosphor waveguide, project the luminescent light away from the crystal phosphor waveguide.

Illumination system with crystal phosphor mechanism and method of operation thereof

An illumination system includes an input device configured to generate a first luminescent light beam; a pumping assembly, optically coupled to the input device, configured to project a pumping light beam into the input device; a focusing lens, aligned with the first luminescent light beam, to focus the first luminescent light beam enhanced by the pumping light beam as an output beam; and an output device, optically coupled to the focusing lens, configured to: receive the output beam from the focusing lens, and project an application output, formed with the output beam, from a projection device.

Illumination system with high intensity projection mechanism and method of operation thereof

An apparatus for managing a memory having a plurality of command/address pins is provided. The apparatus includes a command generating module and a control module. The command generating module generates a set of target commands. The set of target commands include a plurality of command groups. Each of the command groups corresponds to at least one command/address pin of the plurality of command/address pins. It is known that the memory accesses the set of target commands from the plurality of command/address pins at a target time point. The control module controls the command groups to have different transition times prior to the target time points when the command groups are transmitted on the plurality of command/address pins.

Apparatus and method for managing memory

A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

Timing controller for image display and associated control method

A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.

Memory controller and associated signal generating method

A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2(where L and x are positive integers), an (x+1)bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.

Memory controller and associated method for generating memory address

A dynamic memory signal phase tracking method is provided. The method, applied to a memory controller that accesses a memory module, includes: issuing a memory access command and an access request to an arbiter to request for an access right of the memory module; when the access right is obtained, forwarding the memory access command to the memory module and asserting a flag signal; during a period of asserting the flag signal, sequentially using a plurality of candidate delay phases to adjust a memory signal for latching test data from the memory module, determining a delay phase according to latching results corresponding to the candidate delay phases, and recording the determined delay phases; updating an optimal delay phase according to the determined delay phase; and accessing the memory module according to the updated optimal delay phase.

Growing community of inventors

Hsinchu, Taiwan

Yung Peng Chang