Novatek Microelectronics Corp.

Yung-Lung Chen

Jen-Ta Yang

David Shiung

Chia-Jung Yang

Yuan-Tung Peng

Yih-Min Tu

Fan-Chung Lee

Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.

Addressing method and structure for multiple chips and display system thereof

A structure of embedded memory unit with loader comprises a main memory area and an information area as a part of the main memory area. A plurality of loader-program parts is dispersedly stored in different addresses of the main memory area, wherein the loader-program parts are combined to form a complete loader. A loader mapping area is used to store the loader-program during the boot stage. When the boot sequence starts, the original information stored in the loader mapping area is temporarily backup to a temporary space; and the released space is used to store the loader-program. After the boot sequence is completed, the original information is moved back to the original location.

Structure of embedded memory unit with loader and system structure and operation method for the embedded memory apparatus

A voltage controlled oscillator (VCO), suitable for use in a frequency shift keying (FSK) system. The VCO device comprises a switching varactor unit, having a first terminal and a second terminal, wherein the switching varactor unit produces a capacitance, according to a frequency-selection voltage. A VCO core has a first output terminal, a second output terminal complementary to the first output terminal, and an input terminal. Wherein, the switching varactor unit is coupled in parallel with the VCO core at the first output terminal and the second output terminal to produce a capacitance effect with respect to the capacitance, so as to adjust a frequency constant &#x221a;{square root over (LC)} of the VCO core.

Voltage controlled oscillator (VCO) suitable for use in frequency shift keying (FSK) system

An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.

Algorithm of bit synchronization for a digital FSK correlation receiver

A frequency shift key decoding apparatus, having a frequency divider, a signal frequency splitter, and a demodulator. The signal frequency splitter has a frequency synthesizer, (n&#x2212;1) first mixers, n second mixers, and n filters, where n is an integer equal to or larger than 2. The present invention can be applied to a multi-function wireless receiver that supports multiple peripherals. Since a plurality of local carrier signals is generated by only (n&#x2212;1) mixers, the frequency of the local carrier signals can be randomly changed. As the mixers occupy a very small area of the integrated circuit chip, the fabrication cost is low. Further, since the mixers are easily implemented using a digital circuit, the frequency shift key decoding apparatus, and even the whole wireless receiver can be implemented in a single chip.

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Taipei, Taiwan

Yung-Lung Chen