Realtek Semiconductor Inc.

Au Optronics Corporation

Auo Display Plus Corporation

Yung-Jen Chen

Yu-Lan Lo

Shu-Yi Kao

I-Hsiu Lo

Hong-Ming Chen

Chia-Hung Chen

Chung-Kuan Ting

Hsing-Han Tseng

Chien-Huang Liao

Wen-Hao Hsu

Kun-Cheng Tien

Jia-Long Wu

Chihtung Chen

Te-Ming Kuo

Ming-Chi Hung

Yi-Te Yeh

Sheng-Kai Hsu

Hung-Min Shih

Hsin-Hsuan Lo

Chieh-Teng Chang

Hui-Ling Wang

A circuit verification method, including the following steps: inputting a circuit design data to a processor, wherein the circuit design data includes a plurality of logic circuits and a plurality of detection nodes, each logic circuit includes a control terminal and a plurality of input terminals, and is configured to output a signal to the detection node; inputting a plurality of first-stage property command to the processor to generate a plurality of first-stage formal commands, and the first-stage formal commands are configured to verify whether signals of the detection nodes remain stable when a signals of the control terminal of each of the logic circuits does not changed; finding a first part of the detection nodes by a formal method according to the first-stage formal commands; and finding a second part of the detection nodes by a formal method.

Circuit verification method

A display includes an outer frame, a supporting frame, a display module, and a covering member. The supporting frame is accommodated in the outer frame. The display module is disposed on a supporting member of the supporting frame. The supporting member extends toward a display region of the display module from the supporting frame. On a first surface of the display module, a projection area of the supporting member and a projection area of an first optical film of the display module are partially overlapped with each other. A third surface of the covering member is closely attached to a second optical film of the display module. The covering member has an extension portion. The extension portion extends from a fourth surface opposite to the third surface toward a direction away from the third surface, and the extension portion is coplanar with the outer side surface of the outer frame.

Display

An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Integrated circuit simulation and design method and system thereof

The display system comprising a main control module and a display module is provided. The main control module comprises a display driving circuit and a timing control circuit. The display driving circuit is used to output a display driving signal. The timing control circuit is coupled to the display driving circuit to receive the display driving signal, and convert the display driving signal into a digital signal. The display module comprises a first display panel to an N-th display panel, coupled to the timing control circuit and receiving the digital signal, so as to display corresponding multimedia content according to the digital signal, wherein N is a positive integer greater than 1, and the main control module is independently coupled to the display module.

Display system and display array

A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Clock deadlock detecting system, method, and non-transitory computer readable storage medium

The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

Testing method and testing system

A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.

Method of detecting a circuit malfunction and related device

A display panel includes a driver, X data lines, Y scan lines, and X*Y pixels. The driver is configured to receive display data with X*Y resolution. The X data lines are electrically connected to the driver and configured to receive a plurality of pixel voltages. The X*Y pixels are electrically connected to the data lines and the scan lines. When each gray level of a first color display data set is identical and lower than a first threshold value, the pixel voltages of the plurality of first color subpixels are not identical.

Dual gamma display panel

A driving method of pixels of a display panel is provided, which is adapted to drive a pixel of the display panel corresponding to a target grey-level of a display frame. In this method, a first pixel voltage is applied to the pixel during a first display period. At least one second pixel voltage is applied to the pixel during a second display period. The first and second display periods correspond to the display frame, and an enabling duration of the second display period is longer than the enabling duration of the first display period. When the target grey-level is not equal to a limit grey-level, the grey-level corresponding to the pixel voltage is different from the grey-level corresponding to the second pixel voltages. A sum of optical effects of the pixel during the first and second display periods is equal to the optical effect of the target grey-level.

Driving method of pixels of display panel

A display panel includes a plurality of pixels, each of the pixels including a main sub-pixel and a secondary sub-pixel; a plurality of first scan lines, each of the first scan lines being coupled to main and secondary sub-pixels of a row of pixels; a plurality of second scan lines, each of the second scan lines being coupled to secondary sub-pixels of a row of pixels; a plurality of first data lines, each of the first data lines being coupled to main and secondary sub-pixels of (N+1)th and (N+2)th rows of pixels; a plurality of second data lines, each of the second data lines being coupled to main and secondary sub-pixels of (N+3)th and (N+4)th rows of pixels; a scan driver for turning on the main and secondary sub-pixels of the pixels; and a data driver for outputting data signals; wherein N is a multiple of 4, and N&#x2267;0.

Growing community of inventors

Hsinchu County, Taiwan

Yung-Jen Chen