Industrial Technology Research Institute

Intellectual Property Innovation Corporation

National Taiwan University

Yung-Hui Yeh

Chih-Ming Lai

Chi-Chang Liao

Chun-Cheng Cheng

Yu-Wu Wang

Hsing-Lung Wang

Huai-Yuan Tseng

Yu-Lung Liu

Wen-Chun Wang

Heng-Yin Chen

Tai-Jui Wang

Chai-Yuan Sheu

Jung-Jie Huang

Cheng-Ju Tsai

Bo-Chu Chen

Cheng-Chung Lee

Chyi-Ming Leu

Shih-Ming Chen

Jia-Chong Ho

Ya-Hsiang Tai

Chien-Jung Huang

Chi-Lin Chen

Fang-Tsun Chu

Ching-Chieh Lin

Chun-Hung Chu

Chen-Chu Tsai

Chien-Ju Lee

Sheng-Po Wang

Shou-En Liu

Jui-Chang Chuang

Lung-Pin Hsin

Hsiao-Chiang Yao

Li-Ching Wang

Chih-Yuan Tseng

Jui-Wen Yang

Yi-Hsun Huang

Ching-Hsuan Tang

Cheng-Che Wu

Jian-Jang Huang

Bou-Chi Chang

Zong-Hua Cai

Chi-Liang Wu

Shih-Hua Hsiao

Kuang-Chung Liu

Ding-Kang Shih

I Hsuan Peng

Cheng-Yueh Chang

Provided is a protective structure including an auxiliary layer and a hard coating layer. The auxiliary layer has a first surface and a second surface opposite to the first surface. The hard coating layer is located on the second surface of the auxiliary layer. The Young's modulus of the auxiliary layer is gradually increased from the second surface to the first surface. An electronic device with the same is also provided.

Protective structure and electronic device with the same

A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5&#xd7;10atoms/cm. A method of manufacturing the thin film transistor is also provided.

Thin film transistor and manufacturing method thereof

A foldable body is adapted to be connected between two neighboring ones of a plurality of supporting units, such that the two neighboring supporting units are moved relative to each other to flatten or bend a flexible display panel mounted on a supporting surface of each of the supporting units. The foldable body includes a main track and a main shaft. The main track is fixedly connected to one of the two neighboring supporting units. The main shaft is fixedly connected to the other of the two neighboring supporting units and is coupled to the main track to be translated and rotated in the main track. The two neighboring supporting units are connected by the foldable body, such that the supporting units are moved, such as being translated, rotated, or both, relative to each other, to bend at least a portion of the flexible display panel.

Foldable body and foldable display apparatus

A flexible electronic device including a first flexible substrate, an electronic component, and a control device is provided. The electronic component includes a conductive layer. The control device includes at least one integrated circuit and a circuit layer set. The circuit layer set includes a plurality of circuit layers and at least one first dielectric layer, and at least a portion of the first dielectric layer is interposed between two adjacent circuit layers. The integrated circuit is electrically connected to the electronic component through the circuit layer set and the conductive layer. At least a portion of the conductive layer and at least a portion of one circuit layer are integrally formed, and the conductive layer and the circuit layer are both disposed on the first flexible substrate. A fabricating method of a flexible electronic device is also provided.

Flexible electronic device and fabricating method thereof

A driver circuit with device variation compensation function and an operation method thereof are provided. The driver circuit includes a pull-up switch unit, an isolating switch and a pull-down switch unit. A first terminal of the pull-up switch unit is coupled to a first voltage. A second terminal of the pull-up switch unit is coupled to an output terminal of the driver circuit. A first terminal of the isolating switch is coupled to the second terminal of the pull-up switch unit. A first terminal of the pull-down switch unit is coupled to a second terminal of the isolating switch. A second terminal of the pull-down switch unit is coupled to a second voltage. The pull-down switch unit has a device variation compensation function.

Driver circuit with device variation compensation and operation method thereof

According to embodiments of the disclosure, a flexible device and a fabrication method thereof are provided. The flexible device has a first area and a second area, and the stiffness of a portion of the first area is greater than the stiffness of the second area. The flexible device may include a flexible substrate and a rigid element. The flexible substrate includes a first surface and a second surface opposite to each other. The second surface has a coarse structure. The surface roughness of the second surface is greater in the first area than in the second area. The rigid element is disposed on the first surface of the flexible substrate and located in the first area. The stiffness of the rigid element is greater than the stiffness of the flexible substrate. A projection area of the coarse structure on the flexible substrate overlaps an area of the rigid element.

Flexible device and fabrication method of flexible device

A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer. The first insulating layer is patterned by using the gate as an etching mask so as to expose the metal oxide semiconductor layer to serve as a source region and a drain region. A dielectric layer is formed on the substrate to cover the gate and the oxide semiconductor layer, where the dielectric layer has at least one of hydrogen group and hydroxyl group. A heating treatment is performed so that the at least one of hydrogen group and hydroxyl group reacts with the source region and the drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region respectively are formed on the dielectric layer.

Semiconductor device and method for manufacturing the same

A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern.

Sensor element array and method of fabricating the same

A photosensor circuit including a first node, a level shifting circuit, a phototransistor and an inverter is provided. The first node has an operation voltage signal. The level shifting circuit is coupled to the first node for biasing the first node, so that the operation voltage signal is biased to an operation biasing level. The phototransistor is coupled to the first node for receiving an optical signal and accordingly generates a first electrical signal by means of controlling the level of the operation voltage signal. The inverter receives the first electrical signal and accordingly generates and outputs a second electrical signal, which indicates the intensity of the optical signal.

Photosensor circuit having a level shifting circuit for biasing a first node with an operation voltage signal and a phototransistor for modulating the level of the operation voltage signal

Methods of fabricating active device array and organic light emitting diode array are provided. A first pattern metal layer is formed over a substrate. An oxide semiconductor layer is formed entirely over the substrate. A first insulation layer covering the first patterned metal layer and the oxide semiconductor layer is formed entirely on the substrate. A second patterned metal layer is formed on the first insulation layer. The oxide semiconductor layer and the first insulation layer is patterned by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer. A second insulation layer is entirely formed on the substrate. A second patterned oxide semiconductor layer is formed over the second insulation layer. A third patterned metal layer is formed over the second insulation layer.

Method of fabricating an active device array and fabricating an organic light emitting diode array

A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern.

Method of fabricating a pixel array

A photo sensing element array substrate is provided. The photo sensing element array substrate includes a flexible substrate and a plurality of photo sensing elements. The photo sensing elements are disposed in array on the flexible substrate. Each of the photo sensing elements includes a photo sensing thin film transistor (TFT), an oxide semiconductor TFT and a capacitor. The photo sensing TFT is disposed on the flexible substrate. The oxide semiconductor TFT is disposed on the flexible substrate. The oxide semiconductor TFT is electrically connected to the photo sensing TFT. The capacitor is disposed on the flexible substrate and electrically connected between the photo sensing TFT and the oxide semiconductor TFT. When the photo sensing element array substrate is bent, it remains unaffected from normal operation.

Photo sensing element array substrate

An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source electrode, the composite semiconductor active layer and the drain electrode; and a gate electrode formed on the gate dielectric layer and corresponding to the composite semiconductor active layer; wherein the composite semiconductor active layer comprises a low carrier-concentration first oxide semiconductor layer and a high carrier-concentration second oxide semiconductor layer.

Oxide semiconductor thin-film transistor

This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.

Microcrystalline silicon thin film transistor and method for manufacturing the same

A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.

Method for fabricating polysilicon film

Growing community of inventors

Hsinchu, Taiwan

Yung-Hui Yeh