Atomera Incorporated

Yung-Hsuan Yang

Hideki Takeuchi

Richard Burton

Nyles Wynn Cody

Keith Doran Weeks

Robert John Stephenson

Yi-Ann Chen

Dmitri Choutov

A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

Semiconductor device including a superlattice and an asymmetric channel and related methods

A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region. The method may further include removing at least some of the pad oxide, cleaning the active region to expose an upper surface thereof and define rounded shoulders of the active region adjacent the STI regions having an interior angle of at least 125&#xb0;, and forming a superlattice on the active region. The superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor circuit including the superlattice.

Method for making semiconductor device including a superlattice and providing reduced gate leakage

A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125&#xb0;. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.

Semiconductor device including a superlattice and providing reduced gate leakage

A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.

Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods

A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

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San Jose, CA, United States of America

Yung-Hsuan Yang