Taiwan Semiconductor Manufacturing Comp. Ltd.

Yung-Hsu Chuang

Yung-Chow Peng

Wen-Shen Chou

Yu-Tao Yang

Jie-Ren Huang

Yun-Ru Chen

Bindu Madhavi Kasina

Chewn-Pu Jou

Chih-Chiang Chang

Fu-Lung Hsueh

Wei-Li Chen

Po-Zeng Kang

Kuang-Kai Yen

Tsung-Hsiung Lee

Fan-ming Kuo

Shih-Hung Lan

Shi-Hung Wang

Huan-Neng Chen

Hsieh-Hung Hsieh

Yi-Hsuan Liu

Chih-chiang Chang

Ming-Cheng Syu

Shu-Chin Tai

A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

High voltage guard ring semiconductor device and method of forming same

Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Automatic generation of layouts for analog integrated circuits

Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Pre-characterization mixed-signal design, placement, and routing using machine learning

Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Automatic generation of sub-cells for an analog integrated circuit

A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Transition cells for advanced technology processes

Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of sub-cells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration; selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.

Semiconductor device including regions for reducing density gradient effect and method of forming the same

A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.

Method and system for fabricating integrated circuit with aid of programmable circuit synthesis

A method including the operations of receiving a preliminary device layout including a plurality of active areas, analyzing the preliminary device layout to identify empty areas between the plurality of active areas, determining the configurations of the active areas bordering the empty areas, selecting a transition cell from a transition cell library in which the transition cell has a transitional configuration for reducing density gradient effects in the active areas adjacent the transition cell, and inserting the transition cells into the empty areas to define a modified device layout.

The present disclosure describes a method for replacing a device with a cell structure having a plurality of uni-gates. An exemplary method includes receiving a circuit diagram that includes the device, determining the cell structure wherein a cumulative effective gate length of the plurality of uni-gates is equal to a gate length of the device, generating, based on the cell structure and the device, a floor plan that includes an arrangement of a plurality of placeholders that match an arrangement of the cell structure and an arrangement of the device in the circuit diagram, and generating a circuit layout based on the floor plan, the cell structure, and the circuit diagram. The plurality of placeholders is replaced by the cell structure and the cell structure is connectable to other parts of the circuit diagram based on the circuit diagram.

Uni-gate cell design

A method for fabricating a semiconductor structure is provided. The method includes assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell according to a predetermined criterion, wherein the unit cell characterized by the set of parameter values has a circuit characteristic meeting the predetermined criterion; generating a unit cell layout of the unit cell according to the unit cell schematic; generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively; and fabricating the integrated circuit according to the circuit layout.

Growing community of inventors

Hsinchu, Taiwan

Yung-Hsu Chuang