United Microelectronics Corp.

Yung-Feng Cheng

Chia-Wei Huang

Ming-Jui Chen

Wei-Cyuan Lo

Yi-Wei Chen

Ching-Wen Hung

Chih-Sen Huang

Chun-Hsien Huang

Yu-Tse Kuo

Shu-Ru Wang

Li-Ping Huang

Chien-Heng Liu

Hsin-Jen Yu

Shih-Fang Tzou

Yi-Hui Lee

Jia-Rong Wu

Chia-Lin Lu

Ying-Cheng Liu

Hui-Fang Kuo

Tan-Ya Yin

Yi-Kuan Wu

Tsung-Yeh Wu

Chian-Ting Huang

Chung-Yi Chiu

Chin-Lung Lin

Cheng-Te Wang

Te-Hung Wu

Yu-Shiang Yang

Jing-Yi Lee

Chuen Huei Yang

Shih-Ming Kuo

Yueh-Lin Chou

Shu-Yen Liu

Pai-Chi Chen

Hsiang-Yun Huang

Lun-Hung Chen

Wei Cyuan Lo

Kuei-Hsu Chou

Min Cheng Yang

Yu-Chang Lin

Chih-I Wei

Chain-Ting Huang

A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.

Semiconductor device with a single diffusion break structure and a gate structure having aligned sidewalls

Method for fabricating a fin with minimal length between two single-diffusion break (SDB) trenches

A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

Pattern decomposition method

An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Optical proximity correction device and method

Semiconductor device with a single diffusion break structure having a sidewall aligned with a gate sidewall

The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.

Method of designing a layout of a static random access memory pattern

A manufacturing method of a semiconductor device includes the following steps. Trenches are formed on a substrate, and the trenches are formed on a first region and a second region defined on the substrate. A barrier layer is formed conformally in the trenches. A first pull-down process is performed to the barrier layer on the second region. The barrier layer on the first region is covered by a first mask during the first pull-down process. A second pull-down process is performed to the barrier layer on the first region. The barrier layer on the second region is covered by a second mask during the second pull-down process. A proportion of an area of the trenches on the first region to an area of the first region is different from a proportion of an area of the trenches on the second region to an area of the second region.

Manufacturing method of semiconductor device having replacement gate in trench

A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.

Method for correcting bevel corners of a layout pattern

A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.

Method for generating masks for manufacturing of a semiconductor structure

A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.

Method for generating masks for manufacturing of a semiconductor structure and method for manufacturing a semiconductor structure using the same

A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.

Method of forming photomask

Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Dummy gate technology to avoid shorting circuit

A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Method of forming semiconductor structure

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

Semiconductor layout structure

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Kaohsiung, Taiwan

Yung-Feng Cheng