Visteon Global Technolgoies, Inc.

Yung Da Wang

J William Whikehart

John Elliott Whitecar

A timing signal is regenerated from an encoded digital signal having a data clock frequency Rin a receiver using a predetermined sample rate F, wherein the data clock period 1/Ris not an integer multiple of the predetermined sample period 1/F. The method comprises generating an input pulse signal in response to the encoded digital signal. Each of the input pulse signals is accumulated in a predetermined delay element which stores an accumulated value, wherein the predetermined delay element is in a delay loop including N delay elements each having a respective accumulated value. The accumulated values are circulated within the delay loop by shifting at each of the sample periods according to a predetermined shift sequence, the predetermined shift sequence including a plurality of single shifts and at least one other shift size to provide a number of shifts N+&#x3b4; during a cycle of N sample periods. A synchronization pulse is generated in response to the accumulated values and a predetermined threshold. A counter is operated to output the timing signal in response to the predetermined sample rate F, the counter having a variable counter period according to a predetermined counter sequence. The variable counter period has an average over time corresponding to the data clock period 1/R. The counter is reset in response to the synchronization pulse (if synchronization becomes necessary).

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West Bloomfield, MI, United States of America

Yung Da Wang