Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Yung-Chung Chen

Liang-Guang Chen

Chi-Jen Liu

Shich-Chang Suen

Li-Chieh Wu

He Hui Peng

Mei-Yun Wang

Chii-Ming M Wu

Ming-Ta Lei

Fang-Cheng Chen

Chia-Han Lai

Huang-Ming Chen

Wen-Chi Tsai

Chia-Ho Chu

Chih-tang Peng

A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first/second set of signal traces is coupled with the first and third parts of the first/second set of signal traces. All the third parts are in the first signal layer and parallel.

Layout of signal traces

A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.

Semiconductor structure and method for forming the same

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a HPOsolution.

Method for metal gate surface clean

Inductor-capacitor oscillators and common mode resonators are provided. The inductor-capacitor oscillator includes a first transistor, a second transistor, an inductor, a first capacitor, a second capacitor, a first winding, and a second winding. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal and a sixth terminal. The first, second and third terminals are electrically connected to the fifth, fourth and sixth terminals, respectively. The first capacitor and the inductor are coupled between the first terminal and the fourth terminal. The second capacitor is coupled between the third terminal and a reference voltage. The first winding is coupled between the third terminal and the reference voltage. The second winding is coupled between the third terminal and the reference voltage. The first winding and the second winding are symmetric to each other.

Inductor-capacitor oscillator and common mode resonator

Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving a second input signal and thereby outputting a first output signal to a first output terminal; and a latch circuit coupled between the first and second output terminals. The upper circuit is coupled between a high voltage terminal and the buffer circuit and transmits current to the first and second output terminals according to each of the first and second input signals. The lower circuit is coupled between the buffer circuit and a low voltage terminal and withdraws current flowing through the first and second output terminals according to each of the first and second input signals.

Duty cycle corrector

A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Semiconductor device and method for forming the same

Method for cleaning metal gate surface

Growing community of inventors

Hsinchu, Taiwan

Yung-Chung Chen