Via Technologies, Inc.

Yung-Chung Chang

You-Ming Chiu

Chun-Chih Yang

Shu-Tzu Wang

An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nlayer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nlayer, respectively. (b) A buffering device for the N+1layer is implemented at a location close to the middle place between two buffering devices for the Nlayer, and each one of the buffering devices for the Nlayer is electrically connected to the corresponding one of the buffering devices for the N+1layer, respectively. Then, the number of the buffering devices for the N+1layer is judged whether or not to be 1. If it is, then the buffering device for the N+1layer is connected to the signal source root and the method goes to end. If it is not, the method goes to the step (c). In the step (c), the quantity of the parameter N is added by 1, and then the method repeatedly performs the step (b).

Implementing method for buffering devices

An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the N layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the N layer, respectively. (b) A buffering device for the N&plus;1 layer is implemented at a location close to the middle place between two buffering devices for the N layer, and each one of the buffering devices for the N layer is electrically connected to the corresponding one of the buffering devices for the N&plus;1 layer, respectively. Then, the number of the buffering devices for the N&plus;1 layer is judged whether or not to be 1. If it is, then the buffering device for the N&plus;1 layer is connected to the signal source root and the method goes to end. If it is not, the method goes to the step (c). In the step (c), the quantity of the parameter N is added by 1, and then the method repeatedly performs the step (b).

Implementing for buffering devices in circuit layout to ensure same arriving time for clock signal from source root to output bonding pads

The invention provides a method of placement and routing for an array device in an integrated circuit (IC). In the method, a schematic script file used to describe placement for the array device is created according to a netlist and an array structure specification. The schematic script file is loaded into an auto P&R tool. The auto P&R tool is executed for completely routing the array device. After routing, an RC extraction can be directly implemented. Thus, product development time is greatly shortened.

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Shindian, Taiwan

Yung-Chung Chang