Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

Yung-Chow Peng

Wen-Shen Chou

Jaw-Juinn Horng

Chung-Chieh Yang

Yu-Tao Yang

Po-Zeng Kang

Chih-Chiang Chang

Jui-Cheng Huang

Chung-Peng Hsieh

Chin-Ho Chang

Yung-Hsu Chuang

Tai-Yi Chen

Tung-Tsun Chen

Szu-Lin Liu

Chin-Hua Wen

Chung-Ting Lu

Yung-Shun Chen

Chung-Hui Chen

Chih-Hsien Chang

Yi-Shao Liu

Chih-chiang Chang

Yun-Ru Chen

Ching-Ho Chang

Felix Ying-Kit Tsui

Nai Chen Cheng

Yu-Wei Lin

Amit Kundu

Jie-Ren Huang

Fu-Lung Hsueh

Wen-Hung Huang

Yi-Wen Chen

Chien-Hung Zordius Chen

Shi-Tron Lin

Wei-Ting Lin

Chien-Wen Chen

Mu-Jen Huang

Min-Shueh Yuan

Tsung-Hsin Yu

Chung-Kai Lin

Bindu Madhavi Kasina

Chih Chi Hsiao

Brady Yang

Shih-Cheng Yang

Chewn-Pu Jou

Harry-Hak-Lay Chuang

Der-Chyang Yeh

Ruey-Bin Sheen

Chih-Ping Chao

Chia-Lin Yu

Ying-Yu Hsu

Szu-Chun Tsao

Sa-Lly Liu

Chih Ming Yang

Gwo-Shu Chiou

Kuo-Tung Sung

Yu-Chun Lin

Chia-Chung Chen

Ta-Lee Yu

Chung-Min Fu

Wan-Yu Lo

Jinn-Yeh Chien

Wan-Te Chen

Bar-Chung Hwang

Ya Yun Liu

Yi-Hsiang Wang

Kuan-Yu Lin

Bei-Shing Lien

Yi Wei Lu

Chen-Ting Ko

Jizoo Lin

Chih-Ming Yang

Kuo-Liang Deng

Po-Yu Lai

Renjeng Chiang

Li-Yueh Wang

Nang Ping Tu

Jui-Chiang Wang

Kou-Hwa Yu

Ming-Cheng Syu

Ching-Ting Lu

Shu-Chin Tai

Chung-chieh Yang

Shang Hsien Yang

An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Integrated circuit and method for manufacturing the same

A device includes an electrical circuit. The device further includes a first conductive pillar over a first side of a substrate. The device further includes a first conductive rail electrically connected to the first conductive pillar, wherein the electrical circuit is electrically connected to the first conductive rail by the first conductive pillar. The device further includes a power pillar extending through the substrate, wherein the power pillar is electrically connected to the first conductive rail.

Power cell for semiconductor devices

A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated in response to the core voltage either at the disabling voltage level or at the enabling voltage level.

Power on control circuits and methods of operating the same

In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.

Stack-gate circuit

A semiconductor device includes a plurality of active area structures extending in parallel, first and second dummy gate layers spanning the plurality of active area structures, a first active device including first portions of the plurality of active area structures between the first and second dummy gate layers, a metal layer spanning the plurality of active area structures between the first and second dummy gate layers, and a pair of vias positioned at opposite ends of the metal layer. A first via of the pair of vias is configured to be electrically connected to ground, and a second via of the pair of vias is configured to be electrically connected to a current source and a circuit configured to measure a voltage at the node.

Temperature monitoring device and method

A semiconductor device includes a plurality of transistors, a plurality of metal layers, and a resistor. The plurality of transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The plurality of metal layers are overlaid above the plurality of transistors. The resistor is implemented between two of the plurality of metal layers.

Semiconductor device with source resistor

A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

High voltage guard ring semiconductor device and method of forming same

An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.

Integrated circuit device, method, layout, and system

A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain/source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain/source paths connected in series to each other and to the first drain/source paths and having second gates connected to each other and to the first gates.

Low noise ring oscillator devices and methods

A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.

Delay-locked loop circuit and method

A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.

Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Automatic generation of layouts for analog integrated circuits

A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.

Delay measurement system and measurement method

Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Voltage amplifier based on cascaded charge pump boosting

A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Middle end of line decoupling capacitors for semiconductor devices and methods of manufacturing thereof

Growing community of inventors

Hsinchu, Taiwan

Yung-Chow Peng