Etron Technology, Inc.

Realtek Semiconductor Inc.

Piecemakers Technology, Inc.

Yung-Ching Hsieh

Tah-Kang Joseph Ting

Chun Shiah

Bor-Doou Rong

Gyh-Bin Wang

Jeng-Tzong Shih

Yin H Lieu

Chung-Wei Hsieh

Jian-Jun Zhou

A communication system includes an antenna, a first wireless communication circuit, a second wireless communication circuit, a switching circuit, and a control circuit. During a second mode, a transmission and reception period of the antenna is divided by the control circuit into a plurality of first scheduling periods and a plurality of second scheduling periods interleaved with the first scheduling periods. The control circuit controls the switching circuit to select the first path or the second path to connect the antenna to the first wireless communication circuit or the second wireless communication circuit, according to a second priority sequence and a third priority sequence during the first scheduling periods and the second scheduling periods, respectively. The second priority sequence is different from the third priority sequence.

Communication system and communication method

A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.

Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system

A reciprocating or ping-pong voltage boosting circuit is described. The ping-pong boosting circuit has a first and a second boost circuit connected between the power supply voltage source and a ground reference point to generate a first instance and a second instance of a boost voltage. The reciprocating circuit has a switching circuit to alternately place the first and second instance of the boost voltage upon the signal line to bring the voltage level of the signal line to that of the boost voltage. A boost control circuit will provide a switching signal that will control the alternate placing of the first and second instances of the boost voltage upon the signal line. The boost control circuit will provide a boost signal that will cause the first and second boost circuits to generate the first and second instances of the boost voltage.

Ping-pong boost circuit

The invention describes a technique in which the performance of a block write operations for SGRAM and VRAM are improved. The technique also produces improved noise margin along the data line when connecting to bit switches under mask during block write operation. The technique rearranges the physical location of each bit switch located along the data lines such that the worse case configuration is not clustered at the end of the data lines during a block write operation. This reduces the voltage drop along the data lines and provides more energy to switch bit lines or the corresponding memory columns. It also produces less drop on the bit lines as a result of doing a mask during the block write operation.

Distributed bit switch logically interleaved for block write performance

Circuits and methods are disclosed for a row activation control logic for memory arrays. This invention utilizes a row activation control circuit and a NOR gate, in conjunction with a previously disclosed timing reference circuit, to allow the shortening of the row precharge time, yet insuring that the bitline is getting charged well enough without causing the chip to read wrong data at the next row activation. The circuits and methods disclosed can be applied to different types of dynamic random access memories.

Semiconductor memory arrays

A high speed clock-positive edge detection circuit with chip select control that produces a glitch-free transition detection pulse is described. The circuit comprises Logic, Conditioning and Output Sections. An n-channel transistor is connected between output C, output B and the Chip Select input. This eliminates glitches that would otherwise be present, as in the prior art.

High speed glitch-free transition detection circuit with disable control

A buffer memory system provides independent memory blocks, each with independent addressing and data paths, for a processor and input and output devices. The processor can configure the data paths so that an input device can initially supply data to a first memory block. The processor can then assign a second block for input and operate on the data in the first block. The processor can store the results of the process in a third block that has been assigned to an output device. The memory blocks and the associated data paths can paired for operating with a processor with a wider data bus.

Growing community of inventors

Hsinchu, Taiwan

Yung-Ching Hsieh