Taiwan Semiconductor Manufacturing Comp. Ltd.

Yung-Chin Hou

Li-Chun Tien

Lee-Chung Lu

Ta-Pen Guo

Yi-Kan Cheng

Shyue-Shyh Lin

Chung-Hsing Wang

Yuan-Te Hou

Chung-Cheng Wu

Min Cao

Hsiang-Jen Tseng

Hsiao-Shu Chao

Ali Keshavarzi

Ru-Gun Liu

Chih-Ming Lai

Yun-Han Lee

Jung-Chan Yang

Shine Chung

Chun-Hui Tai

Shu-Min Chen

Kuang-Hung Chang

Yu-Chun Wu

Ping Chung Li

Yi-Lin Chuang

Ke-Ying Su

Ting Yu Chen

Tsong-Hua Ou

Ching-Fang Chen

Wei-Li Chen

Kun-Lung Chen

Yao-Ching Ku

Ying-Chou Cheng

Wei-Pin Changchien

Chung-Kai Lin

Shu-Hui Sung

Lie-Szu Juang

Ping-Heng Yeh

Min-Hong Wu

Chu-Ping James Wang

Hui-Zhong Zhuang

Sandeep Kumar Goel

David Barry Scott

Pin-Dai Sue

Chen-Lin Yang

Gwan Sin Chang

Yuh-Jier Mii

Tzu-Ying Lin

Chung-hsing Wang

Jung-chan Yang

Ting-Yu Chen

Hung-Yi Liu

Kun Lung Chen

George H Chang

Kuo-Tung Sung

Helen Shu-Hui Chang

Lee-Chung Yu

Sheng-Hsin Chen

Chen-Teng Fan

Xiang-Dong Chen

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Integrated circuits and manufacturing methods thereof

An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

Integrated circuit with thicker metal lines on lower metallization layer

A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.

Semiconductor layout with different row heights

An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

An IC structure includes first, second, third and fourth transistors on a substrate, and first and second metallization layers over the transistors. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction. One or more of the first metal lines are part of a first net electrically connecting the first and second transistors. The second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction and less than the first line width. One or more of the second metal lines are part of a second net electrically connecting the third and fourth transistors, and a total length of the second net is less than a total length of the first net.

Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

Machine-learning design enablement platform

A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.

Method of component partitions on system on chip and device thereof

Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.

Integrated circuit design in optical shrink technology node

A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

Method of generating RC technology file

Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

Integrated circuit design using DFM-enhanced architecture

A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.

Integrated circuit layouts with power rails under bottom metal layer

Growing community of inventors

Taipei, Taiwan

Yung-Chin Hou