Taiwan Semiconductor Manufacturing Comp. Ltd.

Darfon Electronics Corporation

Yung-Chih Wang

Tai-I Yang

Tien-Lu Lin

Cheng-Chi Chuang

Chen Yang

Chia-Hung Liu

Yu-Chun Hsieh

Yu-Chieh Liao

Hsin-Ping Chen

Hsiang-Lun Kao

Shau-Lin Shue

Chia-Tien Wu

Hsiang-Wei Liu

Jian-Hua Chen

Tze-Liang Lee

Chung-Ting Ko

Wei-Chen Chu

Chunyao Wang

Han-Chi Lin

Po-Hsiang Huang

Dian-Hau Chen

Cheng-Lin Huang

Shin-Yi Yang

Chih-Wei Lu

Zhen-Cheng Wu

Yuh-Jier Mii

Nai-Wei Liu

Shu-Hui Su

Ching Yu Huang

Carlos H Diaz

Kuo-Hua Pan

Ta-Chun Lin

Wen-Huei Guo

Kuei-Ming Chang

Rei-Jay Hsieh

Li-Te Chang

Chih-Yao Chi

Buo-Chin Hsu

Yen-Hsiao Lin

Ching-Yu Wang

A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Semiconductor device and method of manufacture

A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Method of modulating stress of dielectric layers

A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.

Gate all around device

A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Metal line structure and method

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.

Interconnect structure with air-gaps

Stress modulation for dielectric layers

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.

A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer.

Fabrication of gate all around device

A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.

Semiconductor device and manufacturing method thereof

An optical keyswitch includes a keycap, a supporting mechanism having a protrusion disposed under the keycap to support the keycap to move downward or upward, and a switch module including a circuit board, an emitter, and a receiver. The emitter and the receiver are electrically connected to the circuit board. The emitter emits an optical signal to the receiver. When the keycap is not pressed, the receiver receives the optical signal of a first intensity. When the keycap is pressed, the protrusion moves along with the keycap, and the protrusion changes the optical signal received by the receiver to have a second intensity different from the first intensity, so the switch module is triggered to generate a triggering signal.

Optical keyswitch triggered by support mechanism having at least one rotatable frame enable a protrusion to move along with a key cap

Optical keyswitch

A keyboard includes a plurality of keyswitch structures and an adjusting plate movably disposed under the keyswitch structures. Each of the keyswitch structures includes a tactile feedback member. The adjusting plate includes a plate body and a plurality of adjusting bars protruding from the plate body toward the keyswitch structures and respectively corresponding to the tactile feedback members of the keyswitch structures. When the adjusting plate moves relative to the keyswitch structures, the adjusting bars drive the tactile feedback members to change tactile feedback of the keyswitch structures.

Keyboard keyswitches having adjustable tactile feedback members

Growing community of inventors

Taoyuan, Taiwan

Yung-Chih Wang