Mediatek Corporation

Mediatek Incorporation

Yung-Chieh Yu

Cheng-Hsing Chien

Jia-Yi Xu

You-Ming Chiu

The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Flip-flop for low swing clock signal

A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

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Chu-Pei, Taiwan

Yung-Chieh Yu