United Microelectronics Corp.

Yung-Chieh Kuo

Horng-Bor Lu

Ming-Shing Chen

Yi-Ching Wu

Jeng-Ho Wang

Hsin-Yi Lu

Chi-Piao Cheng

Te-Sung Hung

Yan-Home Liu

Mu-Liang Liao

Yi-Ham Tsou

Cheng-Wei Chen

A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.

Method for planarizing semiconductor device

A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.

Reworking method for integrated circuit devices

A semiconductor wafer has a top surface and an edge bevel surface, and a first material layer and a second material layer are respectively formed on the top surface and the edge bevel surface. A surface chemical mechanical polishing (surface CMP) process is performed to polish and remove portions of the first material layer down to a first thickness, and a rim CMP process is performed to completely remove the second material layer on the edge bevel surface down to the edge bevel surface thereafter to achieve a smooth surface of the edge bevel surface. Finally, a chemical cleaning process is performed to clean the edge bevel surface and the top surface, and the semiconductor wafer is dried thereafter.

All-in-one polishing process for a semiconductor wafer

A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.

Method of fabricating barrier layer

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Yung-Chieh Kuo