Tsinghua University

Yung-Chia Lin

Jenq-Kuen Lee

Chung-Wen Huang

Yi-Ping You

Chung-Lin Tang

Yi-Ping Yu

A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Task scheduling method for low power dissipation in a system chip

A method for scheduling instructions for clustered digital signal processors comprising a plurality of clusters, each cluster including at least two functional units and a first register file having a first unit, a second unit and a single set of access ports shared by the functional units comprises steps of checking whether executing one instruction needs data to be read from the first unit and the second unit of the first register file, generating a copying instruction to transfer data from the first unit to the second unit of the first register file, checking whether there is a prior operation cycle available to perform the copying instruction, scheduling the copying instruction in the prior operation cycle, and scheduling the instruction after the copying instruction.

Method for allocating registers using simulated annealing controlled instruction scheduling

A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.

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Taipei, Taiwan

Yung-Chia Lin