Industrial Technology Research Institute

Yung-Cheng Ma

Chi-Lung Wang

I-Yen Chen

Tengh-Yih Wang

Hsien-Feng Kuo

Yen-Tun Peng

Disclosed is directed to a speed-level calculator and calculating method for dynamic voltage scaling. The speed-level calculator comprises a deadline counter, a shifter, and a fixed-point multiplier. The deadline counter calculates the residual time D from current time to each task deadline for completing an episode. The shifter generates a D' value by shifting the D value to the right for e-m bits, and takes the decimal fraction part of the D&#x2032; value for m bits. The speed-level calculator further comprises a saturation control circuit to detect if an overflow occurs on the D&#x2032; value. According to a pre-calculated parameter &#x3b1;corresponding to each task T, the fixed-point multiplier performs the multiplication of D&#x2032; and &#x3b1;. After completing saturation and rounding on the multiplication result, a corresponding clock period is generated by taking the integer part. This clock period is used as speed-level to switch the processor voltage and frequency.

Speed-level calculator and calculating method for dynamic voltage scaling

An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.

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Hsinchu, Taiwan

Yung-Cheng Ma