Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Materials, Inc.

Yung-Cheng Lu

Chi On Chui

Che-Hao Chang

Wai-Fan Yau

Teng-Chun Tsai

David Wingto Cheung

Wan-Yi Kao

Farhad K Moghadam

Hui-Lin Chang

Syun-Ming Jang Jang

Ralf B Willecke

Shin-Puu Jeng

Tai-Chun Huang

Robert Parkash Mandal

Wen-Kai Lin

Michael S Barnes

Tetsuya Ishikawa

Zhen-Cheng Wu

Tze Wing Poon

Chih-Tang Peng

Shen-Nan Lee

Chunyao Wang

Hung Cheng Lin

Ting-Gang Chen

Tien-I Bao

Chung-Chi Ko

Kuo-Yin Lin

Ying-Tsung Chen

Chen-Hua Douglas Yu

Tze-Liang Lee

Li-Qun Xia

Ellie Y Yieh

Huan-Just Lin

Li-Ting Wang

Cheng-Tung Lin

De-Fang Chen

Chien-Hsun Wang

Kuowei Liu

Keng-Chu Lin

Ying-Ho Chen

Shwang-Ming Jeng

Chih-Chang Hung

Chun-Heng Chen

Chang-Sheng Lin

Sung-En Lin

Tzu-Fang Huang

Wen-Kuei Liu

Lih-Ping Li

Ju-Hyung Lee

Yu-Wei Chou

Nasreen Gazala Chopra

Fu-Kai Yang

Shu-Yuan Ku

Liang-Guang Chen

Chih-Hsien Lin

Ming-Chang Wen

Frederic Gaillard

Shich-Chang Suen

Sen-Hong Syue

Bing-Hung Chen

Ching-Hong Jiang

Mong-Song Liang

Szu-Ying Chen

Ming-Hsing Tsai

Chien-Hao Chen

Hung-Wen Su

Chung-Ting Ko

Lain-Jong Li

Ya-Lan Chang

Yee-Chia Yeo

Shau-Lin Shue

Wen-Chih Chiou

Chao-Cheng Chen

Wei-Yang Lee

Hun-Jan Tao

Jyu-Horng Shieh

Weng Chang

Pei-Ren Jeng

Jr-Jung Lin

Chun-Hung Lee

Tsu Shih

Yuan-Ching Peng

De-Wei Yu

Chen-Nan Yeh

Jiun-Ming Kuo

Yuan-Hung Chiu

Ming-Shih Yeh

Chih-Hsiang Yao

Hui-Chi Huang

Minghsing Tsai

Bo-Cyuan Lu

Peng-Fu Hsu

Gin-Chen Huang

Yen-Chun Huang

Chia-Cheng Chou

Dian Sugiarto

Chih-Chung Chang

Chien-Hsueh Shih

Yi-Hsiu Liu

Shu Ling Liao

In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Methods of forming semiconductor devices

A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

Dummy Fin structures and methods of forming same

A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes forming a dielectric layer, which includes forming an as deposited layer using an atomic layer deposition process, which includes flowing a silicon source precursor into a process chamber at a first flow rate, flowing a carbon and nitrogen source precursor into the process chamber at a second flow rate, and flowing an oxygen source precursor into the process chamber at a third flow rate. A ratio of the first flow rate to the second flow rate to the third flow rate ranges between about one to one to eight and one to one to twelve, and the as deposited layer has a carbon concentration substantially greater than a nitrogen concentration. The method further includes annealing the as deposited layer in an environment including HO to form the dielectric layer.

Semiconductor device structure and methods of forming the same

A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl)CH), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Reducing k values of dielectric films through anneal

A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Nanosheet field-effect transistor device including multi-layer spacer film and method of forming

A method of forming a semiconductor device includes forming a first layer on a semiconductor fin; forming a mask on the first layer, the mask being thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The first layer is thinned along the sidewall of the semiconductor fin using the mask. A second layer is formed on the semiconductor fin, the second layer covering the mask and the first layer. A dummy gate layer is formed on the semiconductor fin and patterned to expose a top surface of the semiconductor fin.

Dielectric layer on semiconductor device and method of forming the same

A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Method for manufacturing semiconductor device including annealing treatment of inner spacer layer

Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Semiconductor device and method of manufacture

A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

Semiconductor device with isolation structure

Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

Semiconductor device including multiple inner spacers with different etch rates and method of making

A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

Nano-FET transistor with alternating nanostructures and method of forming thereof

Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.

Semiconductor device and method

The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Post-formation mends of dielectric features

Reducing K values of dielectric films through anneal

Growing community of inventors

Taipei, Taiwan

Yung-Cheng Lu