Taiwan Semiconductor Manufacturing Comp. Ltd.

Yung-Chen Chen

Hui-Zhong Zhuang

Xiangdong Chen

Jerry Chang Jui Kao

Chi-Lin Liu

Tzu-Ying Lin

Seid Hadi Rasouli

A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

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Hsinchu, Taiwan

Yung-Chen Chen