Microsoft Technology Licensing, LLC

Beijing Youzhuju Network Technology Co., Ltd.

Beijing Zitiao Network Technology Co., Ltd.

Yunfeng Shi

Jian Wang

Dan Li

Yongguang Zhang

Haitao Wu

Chuanxiong Guo

Songwu Lu

Danfeng Zhang

Tao Li

Guohan Lv

Guohan Lu

Hangjian Yuan

Shuai Wang

Jing Xing

Jun Zhou

Yuhui Cao

A processor chip, a method for flexibly accessing data in the processor chip, an electronic device, and a non-transitory storage medium are provided. The chip includes: a memory, configured to store read-in tensor data from outside the processor chip; a storage control unit, configured to control reading elements from the memory according to the tensor operation of the operator to send the elements to a computing unit, where the storage control unit includes an address computing module, and the address computing module computes addresses in the memory in one-layer read loop or multi-layer read loop nest according to the parameter configured that is received by the interface, so as to read the elements from computed addresses and send the elements to the computing unit; and the computing unit, configured to perform the tensor operation of the operator by using the elements received.

Chip, method for flexibly accessing data, device, and medium

A processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates a vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading to-be-processed data. The target operand specifies a target storage location in the memory for writing a processed result. The processor further includes an arithmetic logic unit configured to: read the to-be-processed data from the source storage location of the memory; perform, on the to-be-processed data, an arithmetic logic operation associated with the vector operation specified by the target instruction; and write the processed result to the target storage location of the memory.

Processor, method, device and storage medium for data processing

A convolution operation method, a convolution operation apparatus, an electronic device and a storage medium. The method includes: determining an operation convolution kernel, wherein the operation convolution kernel is obtained on the basis of an initial convolution kernel; adjusting an arrangement mode of input data on the basis of the number of channels of the operation convolution kernel, so as to obtain target data, wherein the size of the target data and the number of channels of the target data are different from the size of the input data and the number of channels of the input data, and the number of channels of the target data is equal to the number of channels of the operation convolution kernel; and performing a convolution operation on the basis of the target data and the operation convolution kernel, so as to obtain a convolution operation result.

Convolution operation method, convolution operation apparatus, electronic device and storage medium

Techniques for improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor are provided. The techniques include obtaining a configuration space for a target parameter; obtaining a computational time model of the processor, the computational time model is a function of the target parameter and a number of computing cores of the processor; traversing the target parameter in the configuration space, and calculating, based on the computational time model, a computational time corresponding to the target parameter that is selected; in response to the target parameter being a k-th parameter with a minimum computational time, determining the target parameter as the k-th parameter; and improving the computing efficiency of the processor by configuring the computational size of each computing core in the processor based on the k-th parameter.

Improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor

Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Server-centric high performance network architecture for modular data centers

A hybrid Butterfly Cube ('BCube') architecture is described herein. The BCube architecture is a server-centric network architectural design, and includes a plurality of servers. Each of the plurality of servers may have multiple network ports and serve not only as an end host, but also an intermediate relay node for other servers. The BCube architecture further includes a plurality of switches which are arranged in multiple levels. Each switch has a certain number of network ports for connecting to the servers. The BCube architecture provides multiple parallel paths between any two servers. A packet source routing protocol and a BCube source routing (BSR) protocol are used to determine which path is used for routing a packet between any two servers.

Hybrid butterfly cube architecture for modular data centers

Growing community of inventors

Beijing, China

Yunfeng Shi