Yangtze Memory Technologies Co., Ltd.

Yunfei Liu

Meng Wang

Lin Chen

A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

Marking pattern in forming staircase structure of three-dimensional memory device

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having insulating layers and conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having interleaved layers over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area. The central marking structure consists of interleaved layers and divides the marking area into a first marking sub-area and a second marking sub-area. A first pattern density of the first marking sub-area is higher than or equal to a second pattern density of the second marking sub-area.

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a marking pattern for controlling a trimming rate of a photoresist trimming process includes a plurality of interleaved layers, the plurality of interleaved layers including at least two layers of different materials stacking along a vertical direction over a substrate. In some embodiments, the marking pattern also includes a central marking structure that divides the marking area into a first marking sub-area farther from a device area and a second marking sub-area closer to the device area, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

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Wuhan, China

Yunfei Liu