Boe Technology Group Co., Ltd.

Chinese Academy of Sciences

Hefei Boe Display Technology Co., Ltd.

Beihang University

Nuctech Company Limited

Yunfei Liu

Wei Zhang

Haizhou Yin

Jian Li

Qi Liu

Benzhi Xu

Chao Li

Jilei Gao

Feng Lu

Xipeng Wang

Hao Chen

Ming Xu

Jing Min Xu

Jun Xu

Jie Yang

Chao Xu

Ji Min Zhang

Hang Xiao

Jincheng Jia

Yonggang Zhang

Keke Zhang

Lu Niu

Bin Luo

Huikang Xu

Baisong Gao

Kun Dong

Xianhui Mao

Kai Yao

Yufeng Wei

A display panel having an active area includes: an array substrate and an opposite substrate disposed opposite to the array substrate. The array substrate includes a first substrate and a conductive structure disposed on the first substrate. The conductive structure is located on a side of the active area. On a side of the conductive structure away from the active area, a side surface of the conductive structure is substantially flush with a side surface of the first substrate. On the side where the conductive structure is located, an edge of an orthographic projection of the opposite substrate on a plane where the array substrate is located is located outside an edge of the array substrate.

Display panel including conductive structure and method for manufacturing the same, and display device

The embodiments of the present disclosure disclose gaze estimation cross-scene adaptation method and device based on outlier guidance. A specific implementation of the method comprises: performing pre-training on a source domain based on a given arbitrary gaze estimation model, to obtain a collaborative learning model group; determining an average collaborative model corresponding to each collaborative learning model in the collaborative learning model group, to obtain an average collaborative model group; generating an outlier corresponding to the collaborative learning model group based on a target image, the collaborative learning model group and the average collaborative model group; using an outlier loss function and the outlier to optimize the collaborative learning model group; using any collaborative learning model in the optimized collaborative learning model group to perform gaze estimation. This implementation can effectively stabilize the cross-domain adaptation process and improve the scalability of the system.

Gaze estimation cross-scene adaptation method and device based on outlier guidance

The embodiments of this disclosure disclose an unsupervised image-to-image translation method. A specific implementation of this method comprises: obtaining an initial image, and zooming the initial image to a specific size; performing spatial feature extraction on the initial image to obtain feature information; inputting the feature information to a style-content separation module to obtain content feature information and style feature information; generating reference style feature information of a reference image in response to obtaining the reference image, and setting the reference style feature information as a Gaussian noise in response to not obtaining the reference image; inputting the content feature information and the reference style feature information into a generator to obtain a target image; and zooming the target image to obtain a final target image. This implementation can be applied to a variety of different high-level visual tasks, and improve the expandability of the whole system.

Unsupervised image-to-image translation method based on style-content separation

The embodiments of the present disclosure relate to the field of display technology, and in particular to a display substrate, a display panel, and a display device. The display substrate includes a first electrode, a first wire, and a second wire; the first electrode is provided with a plurality of slits; the first wire is provided on a side of the first electrode, and a first gap is provided between the first wire and the first electrode, and the first wire being electrically connected to the first electrode; a second wire provided on a side of the first electrode away from the first wire, and a second gap being provided between the second wire and the first electrode; wherein each of the slits is provided with a first end and a second end opposed to each other, and the first end is close to the first wire, and the second end is close to the second wire, and a light-transmitting part of the first end is larger than a light-transmitting part of the second end. The electric field disorder of the first end is better than the electric field disorder of the second, so that the weak zone at the first end is larger than the weak zone at the second end. By increasing the light-transmitting part of the first end, the weak zone at the first end becomes smaller, thereby making the weak zone of the first end is basically the same as the weak zone of the second end.

Display substrate, display panel and display device

A shift register unit, a method of driving a shift register unit, a gate driving circuit, and a display device are disclosed. The shift register unit includes an input circuit and an output circuit. The input circuit is configured to write an input signal of the input terminal to the first node in response to an input control signal, so as to control a level of the first node. The output circuit is configured to receive a clock signal of the clock signal terminal and output a scanning signal through the pixel signal output terminal under control of the level of the first node. The output circuit includes a variable resistor, and the variable resistor is configured to adjust a level of the scanning signal according to a resistance value of the variable resistor.

Shift register unit, method of driving shift register unit, gate driving circuit, and display device

A gate driving unit circuit pair and a driving method thereof, a gate driving circuit and a display device are provided. The gate driving unit circuit pair includes two gate driving unit circuits, each of which includes a first output sub-circuit, a second output sub-circuit, and a coupling and isolation sub-circuit. The coupling and isolation sub-circuit is configured to: if the first output sub-circuit outputs signal, isolate the signal of the first output terminal from the signal of the second output terminal; or else, couple the signal of the first output terminal to the second output terminal.

Gate driving unit circuit pair and driving method thereof, gate driving circuit and display device

A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (); b. forming a fin () on the substrate; c. forming an shallow trench isolation structure () on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer () on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region () under the sacrificial gate vacancy; i. etching the shallow trench isolation structure () under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure () levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.

Method for manufacturing finFET

There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l. planarizing the semiconductor structure formed by the foregoing steps to expose the channel protective layer and forming a first separated gate stack and a second separated gate stack. Comparing with the prior art, control ability of independent-gate-voltage FinFET can be effectively improved and it is good for device performance.

FinFET and method of manufacturing same

A method for manufacturing a semiconductor structure comprises following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; depositing a first metal layer on surfaces of an entire semiconductor structure, and then removing the first metal layer; forming an amorphous semiconductor layer on surfaces of the source/drain regions; depositing a second metal layer on surfaces of the entire semiconductor structure, and then removing the second metal layer; and annealing the semiconductor structure. Accordingly, the present invention further provides a semiconductor structure. The present invention is capable of effectively reducing contact resistance at source/drain regions.

Semiconductor structure and method for manufacturing the same

A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer; selectively etching end portions of the gate dielectric layer to form gaps; and filling a material for the gate dielectric layer into the gaps.

Method for manufacturing semiconductor device by selectively removing end portions of gate dielectric layer and then filling end portions with dielectric layer

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Beijing, China

Yunfei Liu