Texas Instruments Corporation

Yunchen Qiu

Jarrod Eliason

David J Toops

Harold L Davis

Xiao Hong Du

Bill Kraus

Manish Goel

Xiaowei Deng

Clive D Bittlestone

Sharad Kumar Gupta

Yuming Zhu

Rashmi Sachan

Morris D Ward

Sai Zhang

Sunil Kumar Misra

Dharmesh Kumar Sonkar

Anuroop S S R Vuppala

In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

Sense amplifier look-through latch for FAMOS-based EPROM

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Self-latch sense timing in a one-time-programmable memory architecture

Data words to be written to a memory location are delta encoded in multi-write avoidance ('MWA') code words. MWA code words result in no re-writing of single-bit storage cells containing logical '0's' to a &#x201c;0&#x201d; state and no re-writing of logical &#x201c;1's&#x201d; to cells that have already been written once to a logical &#x201c;1.&#x201d; Potential MWA code words stored in a look-up table (&#x201c;LUT&#x201d;) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (&#x201c;delta&#x201d;) between a data word currently stored at the memory location and a new data word (&#x201c;NEW_D&#x201d;) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods

One-time programmable (OTP) Electronically Programmable Read-Only Memories (EPROMs) have been used in a number of applications for many years. One drawback with these OTP EPROMs is that these nonvolatile memories tend to be slow and/or may use a considerable amount of area. Here, however, a bit cell is provided that employs a compact dual cell, which generally includes two OTP cells. These OTP cells are generally arranged in differential configuration to increase speed and are arranged to have a small impact on area.

Area efficient high-speed dual one-time programmable differential bit cell

A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored string in the first segment of the TCAM cells, an evaluation module for generating a search enable signal if the match of the corresponding search bits with the first portion of the stored string is determined, and a second segment of the TCAM cells for determining a match of remaining search bits of the search string with a remaining portion of the stored string in response to the search enable signal.

Segmented ternary content addressable memory search architecture

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to its source to turn if off during boostenig. Transistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuits

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to ists source to turn if off during boostenig. Ttransistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuit

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN) to charge the boosting capacitor (C) to VDD at the end of each memory access and to use a PMOS FET (MPMP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

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Plano, TX, United States of America

Yunchen Qiu