Realtek Semiconductor Inc.

National Yang Ming Chiao Tung University

Yun-Tse Chen

Liang-Wei Huang

Kai-Yin Liu

Shih-Hsiung Huang

Yu-Chang Chen

Hsuan-Ting Ho

Chia-wei Yu

Hsuan-ting Ho

Hao-Chiao Hong

Chi-Hsi Su

Ying-Cheng Wu

Yan-Guei Chen

Po-Han Lin

Kuei-Ying Lu

Tzung-hua Tsai

Shao-Feng Hung

Shi-Ming Lu

The present invention discloses a programmable gain amplifier having mode-switching mechanism. An operational amplifier includes a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to a ground terminal. The output terminal generates an output signal. A variable resistor and a first switch are coupled in series between a first terminal and a second terminal that coupled to the first input terminal. A first variable capacitor and a second switch are coupled in series between the first terminal and the second terminal. A second variable capacitor and a third switch are coupled in series between the first terminal and the ground terminal. A low-pass resistor and a low-pass capacitor are coupled in parallel between the first input terminal and the output terminal. An input resistor is coupled between a signal input terminal and the first terminal to receive an input signal from the signal input terminal. The first, the second and the third switches receive a set of mode-switching signals to switch to form a path or an open-circuit.

Signal receiving apparatus and programmable gain amplifier having mode-switching mechanism

A latch includes at least one first standard cell logic gate and at least one second standard cell logic gate. The first standard cell logic gate includes a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The second standard cell logic gate includes a fourth input terminal, a fifth input terminal, a sixth input terminal, and a second output terminal. The first input terminal and the second input terminal receive a first input signal. The third input terminal receives a first output signal. The first output terminal outputs a second output signal. The fourth input terminal receives the second output signal. The fifth input terminal and the sixth input terminal receive a second input signal. The second output terminal outputs the first output signal.

Latch

The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.

Signal gain tuning circuit and method having adaptive mechanism

An echo cancelling system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a first transmitted signal. The first transmitted signal has a first sampling rate. The echo canceller circuit is configured to generate a second transmitted signal according to the first transmitted signal. The second transmitted signal has a second sampling rate. The second sampling rate is greater than the first sampling rate. The echo canceller circuit is further configured to generate an echo cancelling signal according to the second transmitted signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

Echo cancelling system and echo cancelling method

Parameter calibration method for calibrating multiple parameters corresponding to multiple electronic components to be calibrated in a circuit, including steps: (A) turning off all of the electronic components to be calibrated and selecting a first electronic component from the electronic components to be calibrated as an electronic component being calibrated; (B) turning on the electronic component being calibrated and performing a calibration procedure on the electronic component being calibrated to determine a setting value of a parameter corresponding to the electronic component being calibrated; and (C) selecting a second electronic component from the electronic components to be calibrated as the electronic component being calibrated and performing step (B). Step (C) is repeatedly performed until all of the electronic components to be calibrated have become electronic components that have been calibrated, and when performing step (C), the electronic component(s) that have been calibrated are kept being turned on.

Parameter calibration method and semiconductor device utilizing the same

A time interleaved analog-to-digital converter (TIADC) is provided. The TIADC converts an input signal into a digital output signal and includes N analog-to-digital converters (ADCs), a clock generation circuit, and a control circuit. The N ADCs receive the input signal and sample the input signal according to N sampling clocks to each generate a digital output code, N being an integer greater than or equal to 2. The clock generation circuit is configured to receive a working clock and a set of control values and to generate the N sampling clocks according to the set of control values and the working clock. The control circuit is configured to periodically generate the set of control values based on a pseudo random number and to output the digital output codes in turn as the digital output signal.

Time interleaved analog-to-digital converter

A signal processing circuit, which includes: a first clock source, configured to generate a first clock signal; a phase adjusting circuit, configured to receive the first clock signal, and to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensating circuit, configured to compensate an input signal according to an error signal, to generate an compensated input signal; an error calculating circuit, configured to generate the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end ADC (Analog to Digital Converter), configured to sample the compensated input signal according to the second clock signal.

Signal processing circuit and signal processing method

A filter can perform two filtering processes. The filter includes a switching circuit, a first filter circuit, and a second filter circuit. The first filter circuit is coupled to the switching circuit. The second filter circuit is coupled to the switching circuit. The first filter circuit performs a first filtering process on an input signal according to a state of the switching circuit. The first filter circuit and the second filter circuit work together to perform a second filtering process on the input signal according to the state of the switching circuit.

Filter and operation method

A successive approximation register analog-to-digital converter capable of accelerating reset comprises: a sampling circuit generating at least one output signal(s) according to at least one input signal(s); a comparator generating at least one comparator output signal(s) according to the at least one output signal(s) and a reset signal; a control circuit controlling the operation of the sampling circuit according to the at least one comparator output signal(s) or the equivalent thereof, and generating the reset signal; a first reset wire circuit outputting the reset signal to the comparator so that a first circuit of the comparator is reset when the value of the reset signal is a first value; and a second reset wire circuit outputting the reset signal to the comparator so that a second circuit of the comparator is synchronously reset when the value of the reset signal is the first value.

Successive approximation register analog-to-digital converter capable of accelerating reset

A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.

Growing community of inventors

Hsinchu, Taiwan

Yun-Tse Chen