Other

Cirrus Logic Inc.

Yun-Ti Wang

Jyhfong Lin

He Du

Zhong-Xuan Zhang

A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed. During the mode `off,` the path from current source to ground is completely cut off, so that at this mode there is no power consumption. Prior to turning to the `on` mode, the current source I.sub.B is first turned on to establish a stable current and to bias all the related nodes. The current steering circuitry is then turned to mode `on` to achieve a smooth transition. Similarly, the transition from mode `on` to `off` is achieved by steering the current to ground first and then cutting off the current source. Various embodiments are disclosed.

Low power high speed CMOS current switching circuit

A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1and din2, and generates, in response to a first control signal .PHI..sub.1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal .PHI..sub.2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal .PHI..sub.0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, .PHI..sub.1 and .PHI..sub.2, is such that the second control signal .PHI..sub.2 is activated LOW after a finite period following the initial activation of the first control signal .PHI..sub.1 . The third control signal .PHI..sub.0 is preferably activated LOW when the first and second control signals, .PHI..sub.1 and .PHI..sub.2, are inactive HIGH.

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Fremont, CA, United States of America

Yun-Ti Wang