Samsung Electronics Co., Ltd.

Yun-Sung Lee

Yong-il Kim

Joo-Sung Park

Nam-Jung Kang

Dae-Ik Kim

Gil-Sub Kim

Jai-kyun Park

Jong-seop Lee

A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.

Methods of manufacturing capacitor structures and methods of manufacturing semiconductor devices using the same

Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.

Methods of manufacturing semiconductor device having recess channel array transistor

In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side and bottom surfaces of the first and second sub-trenches, respectively. The second sub-trench has a width greater than the first sub-trench. The first sub-oxide layer has a first thickness that is uniform along the side and bottom surfaces of the first sub-trench and the second sub-oxide layer has a second thickness greater than the first thickness along the side surface of the second sub-trench. A liner layer is formed on the trench oxide layer, and an insulation pattern is formed on the liner layer.

Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same

A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

Growing community of inventors

Gyeonggi-do, South Korea

Yun-Sung Lee