Samsung Electronics Co., Ltd.

Yun-seung Kang

Hyun-chul Lee

Ji-seung Lee

Soung-hee Lee

Sang-gyo Chung

Jin-Hong Kim

Joon Hyuk Kim

Suk-chul Bang

Eun-Kuk Chung

Jun Hyuk Seo

Jae-Seung Hwang

Min-Chul Chae

Woo-Jin Cho

Sang-sup Jeong

Jong-chul Park

Jong-Chul Park

Sung-Un Kwon

Kwang-Yong Yang

Jong-Heui Song

Kyung-Tae Jang

Young-Mi Lee

Seok-Hyun Lim

Jong-Seon Ahn

Hyung-Mo Yang

Chang-Yeon Yoo

An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.

Integrated circuit device and method of manufacturing the same

Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.

Methods of fabricating integrated circuit devices

A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.

Method of forming patterns for semiconductor device

A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

Stacked semiconductor device and related method

Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.

Method of fabricating semiconductor device having metal-semiconductor compound regions

A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

Methods of fabricating semiconductor device including fin-fet

In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.

Semiconductor device and method of manufacturing the same

Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

Method of fabricating semiconductor device having contact hole with high aspect-ratio

Growing community of inventors

Seoul, South Korea

Yun-seung Kang