Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Yun-seok Choi

Hee-Seok Lee

Seung-Kwan Ryu

Tae-Je Cho

Seung-Joo Maeng

Kyoung-sei Choi

Ye-chung Chung

Kyong-Soon Cho

Na-rae Shin

Young-sang Cho

Dae-woo Son

Keung-beum Kim

Chang-Gil Ryu

Jin-Suk Hong

Chang-Sig Kang

Yu-Kyung Park

Geun-Young Song

Byung Chan Ahn

Min-seung Yoon

Jin-Woo Park

Yong-hoon Kim

Sang-Uk Han

Yool Kang

Jae-Wook Yoo

Ji-hwang Kim

Eun-Seok Song

Jong-bo Shim

Seok-hyun Lee

Jae-Chang Lee

Boo-deuk Kim

So-Young Lim

Eun-Seok Lee

Hyo-Chul Lee

Young-Sang Cho

Eun-seok Song

Ye-hwan Kim

Sang-Heui Lee

Hyeok-Man Kwon

Cha-jea Jo

In-won O

Sang-Heul Lee

Soon-Kyoung Kwon

Kyoung-sil Park

Ki-Yeon Chu

A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

Semiconductor package including interposer

An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

Interposer and semiconductor package including the same

A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

Semiconductor package and method of manufacturing the same

Provided is a substrate cleaning apparatus including: a cleaning bath configured to accommodate a substrate having a first surface and a second surface; a substrate support configured to support the substrate; first and second nozzle bars provided in the cleaning bath to be rotatable in a plane parallel with the substrate, each of the first and the second nozzle bars including a passage; a plurality of nozzles provided along a longitudinal direction of each of the first and the second nozzle bars and configured to spray the cleaning solution from the passage of each of the first and the second nozzle bars to the substrate; and first and second brushes, the first brush provided on a first side of the substrate and configured to clean the first surface and the second brush provided on a second side of the substrate and configured to clean the second surface of the substrate.

Substrate cleaning apparatus

A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, an aromatic ring-containing polymer, and a solvent, applying the hardmask composition to an etching target layer, forming a hardmask by heat-treating the applied hardmask composition, forming a photoresist pattern on the hardmask, forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask, and forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask.

Method of forming patterns for semiconductor device

A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

Printed circuit board and semiconductor package including the same

According to example embodiments, an image display panel assembly includes a flexible printed circuit (FPC), an image display panel, at least one gate driver integrated circuit (IC) package, and at least one source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The at least one gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and configured to provide the gate driving signal to gate lines of the plurality of pixels. The at least one source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and configured to provide the source driving signal to source lines of the plurality of pixels.

Source driver, an image display assembly and an image display apparatus

A polishing head includes a substrate carrier to suck and to pressurize a substrate, and a retainer ring secured under the substrate carrier, the retainer ring surrounding a circumference of the substrate and including a cooling channel therethrough to circulate a coolant fluid.

Polishing head and polishing carrier apparatus having the same

A method of manufacturing a semiconductor package includes: providing a package substrate having a first surface and a second surface opposite the first surface; providing a first semiconductor chip on the package substrate, the first semiconductor chip having a first surface facing the second surface of the package substrate, a second surface opposite the first surface of the first semiconductor chip, and lateral surfaces extending from the first surface of the first semiconductor chip to the second surface of the first semiconductor chip; providing a molding layer covering the lateral surfaces of the first semiconductor chip and covering the second surface of the package substrate; and providing a plurality of through-molding conductive vias outside the lateral surfaces of the first semiconductor chip. The through-molding conductive vias may be formed before forming the molding layer and may pass through the molding layer. The through-molding conductive vias may extend beyond a first surface of the molding layer.

Semiconductor chip package and method of manufacturing the same

An apparatus and method reduce power consumption in a broadband wireless communication system. A transmitting end apparatus that includes a plurality of transmit (Tx) antennas includes a control block, a Processor (DSP) block, a modem block, and at least one power controller. The control block determines a traffic amount based on an amount of used resources. The Digital Signal Processor (DSP) block performs scheduling by using a subset of Tx antennas and a subset of resources on a frequency axis if the traffic amount is less than a threshold. The modem block applies boosting to a signal transmitted using the subset of resources. And at least one controller turns off an operation of at least one power amplifier that corresponds to at least one Tx antenna that is not included in the subset of Tx antennas.

Apparatus and method for saving power consumption in broadband wireless communication system

An image display panel assembly includes a flexible printed circuit (FPC), an image display panel, a gate driver integrated circuit (IC) package, and a source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and provide the gate driving signal to the plurality of pixels. The source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and provide the source driving signal to the plurality of pixels.

Growing community of inventors

Hwaseong-si, South Korea

Yun-seok Choi